oc8051_top.srr

8051 IP核VERILOG代码

$ Start of Compile
#Tue Feb 12 22:48:01 2002

Synplicity Verilog Compiler, version 7.0.0, Build 078R, built Aug  8 2001
Copyright (C) 1994-2000, Synplicity Inc.  All Rights Reserved

@I::"D:\verilog\oc8051\disp.v"
@I::"D:\verilog\oc8051\oc8051_acc.v"
@I:"D:\verilog\oc8051\oc8051_acc.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_alu.v"
@I:"D:\verilog\oc8051\oc8051_alu.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_alu_src1_sel.v"
@I:"D:\verilog\oc8051\oc8051_alu_src1_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_alu_src2_sel.v"
@I:"D:\verilog\oc8051\oc8051_alu_src2_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_alu_src3_sel.v"
@I::"D:\verilog\oc8051\oc8051_comp.v"
@I:"D:\verilog\oc8051\oc8051_comp.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_cy_select.v"
@I:"D:\verilog\oc8051\oc8051_cy_select.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_decoder.v"
@I:"D:\verilog\oc8051\oc8051_decoder.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_rom.v"
@I::"D:\verilog\oc8051\oc8051_dptr.v"
@I:"D:\verilog\oc8051\oc8051_dptr.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_ext_addr_sel.v"
@I:"D:\verilog\oc8051\oc8051_ext_addr_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_fpga_top.v"
@I::"D:\verilog\oc8051\oc8051_immediate_sel.v"
@I:"D:\verilog\oc8051\oc8051_immediate_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_indi_addr.v"
@I::"D:\verilog\oc8051\oc8051_op_select.v"
@I:"D:\verilog\oc8051\oc8051_op_select.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_pc.v"
@I:"D:\verilog\oc8051\oc8051_pc.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_port_out.v"
@I:"D:\verilog\oc8051\oc8051_port_out.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_psw.v"
@I:"D:\verilog\oc8051\oc8051_psw.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_ram_rd_sel.v"
@I:"D:\verilog\oc8051\oc8051_ram_rd_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_ram.v"
@I::"D:\verilog\oc8051\oc8051_ram_sel.v"
@I:"D:\verilog\oc8051\oc8051_ram_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_ram_top.v"
@I:"D:\verilog\oc8051\oc8051_ram_top.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_ram_wr_sel.v"
@I:"D:\verilog\oc8051\oc8051_ram_wr_sel.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_reg1.v"
@I::"D:\verilog\oc8051\oc8051_reg2.v"
@I::"D:\verilog\oc8051\oc8051_reg3.v"
@I::"D:\verilog\oc8051\oc8051_reg4.v"
@I::"D:\verilog\oc8051\oc8051_reg5.v"
@I::"D:\verilog\oc8051\oc8051_reg8.v"
@I::"D:\verilog\oc8051\oc8051_rom_addr_sel.v"
@I::"D:\verilog\oc8051\oc8051_sp.v"
@I:"D:\verilog\oc8051\oc8051_sp.v":"D:\verilog\oc8051\oc8051_defines.v"
@I::"D:\verilog\oc8051\oc8051_timescale.v"
@I::"D:\verilog\oc8051\oc8051_top.v"
Verilog syntax check successful!
File D:\verilog\oc8051\oc8051_rom.v changed - recompiling
Selecting top level module oc8051_fpga_top
Synthesizing module oc8051_reg8
Synthesizing module oc8051_reg1
Synthesizing module oc8051_reg2
Synthesizing module oc8051_reg3
Synthesizing module oc8051_reg5
Synthesizing module oc8051_reg4
Synthesizing module oc8051_pc
Synthesizing module oc8051_decoder
@N:"D:\verilog\oc8051\oc8051_decoder.v":2870:0:2870:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Synthesizing module oc8051_ram_rd_sel
Synthesizing module oc8051_ram_wr_sel
Synthesizing module oc8051_alu
Synthesizing module oc8051_immediate_sel
Synthesizing module RAMB4_S8_S8
Synthesizing module oc8051_ram
Synthesizing module oc8051_ram_top
Synthesizing module oc8051_acc
Synthesizing module oc8051_alu_src1_sel
Synthesizing module oc8051_alu_src2_sel
Synthesizing module oc8051_alu_src3_sel
Synthesizing module oc8051_comp
Synthesizing module oc8051_sp
Synthesizing module ROM32X1
Synthesizing module rom0
Synthesizing module rom1
Synthesizing module rom2
Synthesizing module rom3
Synthesizing module oc8051_rom
Synthesizing module oc8051_dptr
Synthesizing module oc8051_cy_select
Synthesizing module oc8051_psw
Synthesizing module oc8051_indi_addr
Synthesizing module oc8051_rom_addr_sel
Synthesizing module oc8051_ext_addr_sel
Synthesizing module oc8051_ram_sel
Synthesizing module oc8051_port_out
Synthesizing module oc8051_op_select
Synthesizing module oc8051_top
Synthesizing module disp
Synthesizing module oc8051_fpga_top
@END
Process took 22.24 seconds realtime, 22.35 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.0.0, Build 078R, built Aug  8 2001
Copyright (C) 1994-2000, Synplicity Inc.  All Rights Reserved
Automatic dissolve at startup in view:work.oc8051_ram_top(verilog) of oc8051_ram1(oc8051_ram)
Automatic dissolve at startup in view:work.oc8051_rom(verilog) of rom_3(rom3)
Automatic dissolve at startup in view:work.oc8051_rom(verilog) of rom_2(rom2)
Automatic dissolve at startup in view:work.oc8051_rom(verilog) of rom_1(rom1)
Automatic dissolve at startup in view:work.oc8051_rom(verilog) of rom_0(rom0)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_rom_addr_sel1(oc8051_rom_addr_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_sp1(oc8051_sp)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_alu_src3_sel1(oc8051_alu_src3_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_alu_src2_sel1(oc8051_alu_src2_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_alu_src1_sel1(oc8051_alu_src1_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_immediate_sel1(oc8051_immediate_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_ram_rd_sel1(oc8051_ram_rd_sel)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_rd_ram(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_op2_dr_reg(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_psw_reg(oc8051_reg2)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg2_cy(oc8051_reg2)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_des1(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg1_wad2(oc8051_reg1)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg1_bit_addr(oc8051_reg1)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_imm(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg4_alu_op(oc8051_reg4)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg5_rn(oc8051_reg5)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_op3(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_ri(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_ram_op(oc8051_reg8)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg3_wr_sel(oc8051_reg3)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg1_wr(oc8051_reg1)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg1_sre_sel3(oc8051_reg1)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg2_src_sel2(oc8051_reg2)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg2_src_sel1(oc8051_reg2)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg1_write(oc8051_reg1)
Automatic dissolve at startup in view:work.oc8051_top(verilog) of oc8051_reg8_pc_hi(oc8051_reg8)
@N:"d:\verilog\oc8051\oc8051_sp.v":78:0:78:5|Found updn counter in view:work.oc8051_top(verilog) inst oc8051_sp1.data_out[7:0] 
Encoding state machine work.oc8051_decoder(verilog)-state_h.state[3:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
Automatic dissolve during optimization of view:work.oc8051_top(verilog) of oc8051_cy_select1(oc8051_cy_select)
Automatic dissolve during optimization of view:work.oc8051_top(verilog) of oc8051_dptr1(oc8051_dptr)
Automatic dissolve during optimization of view:work.oc8051_top(verilog) of oc8051_rom1(oc8051_rom)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

Net buffering Report for view:work.oc8051_fpga_top(verilog):
No nets needed buffering.

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base D:\verilog\oc8051\rev_1\oc8051_top.srm
Writing EDIF Netlist and constraint files
Found clock clk with period 200.00ns 


##### START TIMING REPORT #####
# Timing Report written on Tue Feb 12 22:50:34 2002
#


Top view:              oc8051_fpga_top
Slew propagation mode: worst
Paths requested:       5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.



Performance Summary 
*******************


Worst slack in design: 164.205

                   Requested     Estimated     Requested     Estimated                 Clock   
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type    
-----------------------------------------------------------------------------------------------
clk                5.0 MHz       27.9 MHz      200.000       35.796        164.205     inferred
System             5.0 MHz       43.5 MHz      200.000       22.988        177.012     system  
===============================================================================================



Clock Relationships
*******************

Starting     Ending        r/r           f/f           r/f           f/r   
Clock        Clock      time (ns)     time (ns)     time (ns)     time (ns)
---------------------------------------------------------------------------
clk          clk        200.0         -             -             -        
===========================================================================



Interface Information 
*********************



Input Ports: