latch.txt

门拴电路,4位选择器

用wait语句描述一个门拴电路。当clock=1时q=d.
/*********************************************************
 *	File:	latch.v
 *	Description: This module describe a latch.
 *********************************************************/

module latch (clock, d, q);
    input	clock,		// clock to latch
		d;		// data input
    output	q;		// latch output

    reg		q;

    always @(clock or d) begin	// This @() control is must. Otherwise
	wait(clock);		// the simulation will have dead loop
	q = d;
    end
endmodule

module test;
    reg		d, clock;
    wire	q;

    latch	g(clock, d, q);

    initial begin
	$vcdpluson;
	clock = 0;
	d = 0;
	fork repeat(200) begin
	    #10 clock = !clock;
	end begin
	    #35 d = 1;
	    #50 d = 0;
	end join
	$finish;
    end
endmodule


用三种办法设计一个四输入选择器(4:1 multiplexer) 。使用连续赋值，if-else, case.
/**********************************************************************
 *	File:	mux.v
 *	Description: This file contains 3 modules for 3 implementations
 *		of a 4:1 multiplexer.
 **********************************************************************/

module	mux_1 (a, b, c, d, s, q);
    input	a,		// first input
		b,		// second input
		c,		// third input
		d;		// forth input
    input[1:0]	s;		// select input
    output	q;		// selected signal output

    assign q = s==2'd0 && a || s==2'd1 && b || s==2'd2 && c ||
	       s==2'd3 && d;
endmodule

module mux_2 (a, b, c, d, s, q);
    input	a,		// first input
		b,		// second input
		c,		// third input
		d;		// forth input
    input[1:0]	s;		// select input
    output	q;		// selected signal output

    always @(a or b or c or d or s) begin
	if(s==2'd0)	 q <= a;
	else if(s==2'd1) q <= b;
	else if(s==2'd2) q <= c;
	else if(s==2'd3) q <= d;
	else q <= 1'bx;
    end
endmodule

module mux_3 (a, b, c, d, s, q);
    input	a,		// first input
		b,		// second input
		c,		// third input
		d;		// forth input
    input[1:0]	s;		// select input
    output	q;		// selected signal output

    always @(a or b or c or d or s) begin
	case (s)
	    0: q <= a;
	    1: q <= b;
	    2: q <= c;
	    3: q <= d;
	    default: q <= 1'bx;
	endcase
    end
endmodule]


用case语句设计一个8用途四位ALU。a和b为4-bit输入。out为5-bit输出。指令编码见下表。
/***************************************************************
 *	File:	alu.v
 *	Description: This module is an ALU
 ***************************************************************/

module alu (code, a, b, out);
    input[2:0]	code;		// operating code
    input[3:0]	a,		// first operator
		b;		// second operator
    output[4:0]	out;		// operating result

    reg[4:0]	out;

    always @(code or a or b)
	case (code)
	    0: out = a;
	    1: out = a+b;
	    2: out = a-b;
	    3: out = a / b;
	    4: out = a % b;
	    5: out = a << 1;
	    6: out = a >> 1;
	    7: out = (a > b);
	    default: out = 8'bx;
	endcase
endmodule