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来自「148个verilog hdl小程序（有很多testbench）——.」· 代码 · 共 6 行

# Reading C:/Modeltech_5.5f/win32/../tcl/vsim/pref.tcl 
# vsim {E:\my} {data\教程\FPGA\verilog书配套光盘\source\chap3\count4.v} 
# ERROR: Could not open library work at work: No such file or directory
# ERROR: Could not open library work at work: No such file or directory
# Error loading design