mux2_1a.v

来自「148个verilog hdl小程序（有很多testbench）——.」· Verilog 代码 · 共 9 行

module mux2_1a(out,a,b,sel);
output out;
input a,b,sel;
not (sel_,sel);
and (a1,a,sel_),
    (a2,b,sel);
or  (out,a1,a2);
endmodule