mux21_2.v

来自「148个verilog hdl小程序（有很多testbench）——.」· Verilog 代码 · 共 11 行

module MUX21_2(out,a,b,sel);
input a,b,sel;
output out;
reg out;
always@(a or b or sel)
  begin
     if(sel==0) out=a;
     else       out=b;
  end
endmodule