pic.v

verilog实例 100 多个

integer cycle_counter;
initial cycle_counter = 0;
always @(negedge clk) begin
   if (re) begin
`ifdef DEBUG_SHOWREADS   
      $display ("[%0d] Read:  data = %0h(hex), from bank #%0d(dec) location %0h", cycle_counter, dout, bank, location);
`endif
   end
   if (we) begin
`ifdef DEBUG_SHOWWRITES   
      $display ("[%0d] Write: data = %0h(hex), to   bank #%0d(dec) location %0h", cycle_counter, din, bank, location);
`endif
   end
   if (~reset) cycle_counter = cycle_counter + 1;
end  
// synopsys translate_on

// READ the Register File
//
always @(bank or location or re
		or commonblockout 
		or highblock0out 
		or highblock1out 
		or highblock2out 
		or highblock3out) begin
   if (re) begin		
      if (location[4:3] == 2'b01) begin
         // This is the lower 8 words, common to all banks, just above special registers
         dout <= commonblockout;	// Access to first 8 locations past Special Registers 
      end
      else begin
         if (location[4]) begin
            // Address is in the upper 16 words on one of the 4 banks
            case (bank) // synopsys full_case parallel_case
               2'b00:  dout <= highblock0out;	// Upper 16 words of Bank #0
               2'b01:  dout <= highblock1out;	// Upper 16 words of Bank #1
               2'b10:  dout <= highblock2out;	// Upper 16 words of Bank #2
               2'b11:  dout <= highblock3out;	// Upper 16 words of Bank #3
            endcase
         end
         else begin
            dout <= 8'hff;
         end
      end
   end
   else begin
      dout <= 8'hff;
   end
end

// Initial Write logic.
//
// Generate the specific write enables based on the PIC's bank/location rules.
// The individual memory blocks will do the actual synchronous write.
//
always @(we or bank or location or reset) begin
   if (reset) begin
      commonblocksel <= 1'b0;
      highblock0sel  <= 1'b0;
      highblock1sel  <= 1'b0;
      highblock2sel  <= 1'b0;
      highblock3sel  <= 1'b0;
   end
   else begin
      if (we) begin
         if (location[4:3] == 2'b01) begin
            // This is the lower 8 words, common to all banks, just above special registers
            commonblocksel <= 1'b1;
            highblock0sel  <= 1'b0;
            highblock1sel  <= 1'b0;
            highblock2sel  <= 1'b0;
            highblock3sel  <= 1'b0;
         end
         else begin
            if (location[4]) begin
               // Address is in the upper 16 words on one of the 4 banks
               commonblocksel <= 1'b0;
               case (bank) // synopsys full_case parallel_case
                  2'b00:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b1000; // Upper 16 words of Bank #0
                  2'b01:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0100; // Upper 16 words of Bank #1
                  2'b10:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0010; // Upper 16 words of Bank #2
                  2'b11:  {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0001; // Upper 16 words of Bank #3
               endcase
            end
            else begin
               commonblocksel <= 1'b0;
               highblock0sel  <= 1'b0;
               highblock1sel  <= 1'b0;
               highblock2sel  <= 1'b0;
               highblock3sel  <= 1'b0;
            end
         end
      end
      else begin
         commonblocksel <= 1'b0;
         highblock0sel  <= 1'b0;
         highblock1sel  <= 1'b0;
         highblock2sel  <= 1'b0;
         highblock3sel  <= 1'b0;
      end
   end
end

// *** Buses feeding the memory blocks are driven directly from din.

always @(din)
   commonblockin <= din;

always @(din)
   highblock0in <= din;

always @(din)
   highblock1in <= din;

always @(din)
   highblock2in <= din;

always @(din)
   highblock3in <= din;

// ****************** Common Block *************

reg [7:0]	r8, r9, r10, r11, r12, r13, r14, r15;

// Read from common block
always @(location or
		r8 or r9 or r10 or r11 or r12 or r13 or r14 or r15) begin
   case (location[2:0])
      3'h0: commonblockout <= r8;
      3'h1: commonblockout <= r9;
      3'h2: commonblockout <= r10;
      3'h3: commonblockout <= r11;
      3'h4: commonblockout <= r12;
      3'h5: commonblockout <= r13;
      3'h6: commonblockout <= r14;
      3'h7: commonblockout <= r15;
   endcase
end
      
// Write to common block
always @(posedge clk) begin
   if (we & commonblocksel) begin
      case (location[2:0])
         3'h0: r8  <= commonblockin;
         3'h1: r9  <= commonblockin;
         3'h2: r10 <= commonblockin;
         3'h3: r11 <= commonblockin;
         3'h4: r12 <= commonblockin;
         3'h5: r13 <= commonblockin;
         3'h6: r14 <= commonblockin;
         3'h7: r15 <= commonblockin;
      endcase
   end
end

// **************** Highblock0 ****************

reg [7:0]	r16, r17, r18, r19, r20, r21, r22, r23;
reg [7:0]	r24, r25, r26, r27, r28, r29, r30, r31;

// Read from high block bank0
always @(location or
		r16 or r17 or r18 or r19 or r20 or r21 or r22 or r23 or
		r24 or r25 or r26 or r27 or r28 or r29 or r30 or r31
) begin
   case (location[3:0])
      4'h0: highblock0out <= r16;
      4'h1: highblock0out <= r17;
      4'h2: highblock0out <= r18;
      4'h3: highblock0out <= r19;
      4'h4: highblock0out <= r20;
      4'h5: highblock0out <= r21;
      4'h6: highblock0out <= r22;
      4'h7: highblock0out <= r23;
      4'h8: highblock0out <= r24;
      4'h9: highblock0out <= r25;
      4'hA: highblock0out <= r26;
      4'hB: highblock0out <= r27;
      4'hC: highblock0out <= r28;
      4'hD: highblock0out <= r29;
      4'hE: highblock0out <= r30;
      4'hF: highblock0out <= r31;
   endcase
end
      
// Write to high block bank 0
always @(posedge clk) begin
   if (we & highblock0sel) begin
      case (location[3:0])
         4'h0: r16 <= highblock0in;
         4'h1: r17 <= highblock0in;
         4'h2: r18 <= highblock0in;
         4'h3: r19 <= highblock0in;
         4'h4: r20 <= highblock0in;
         4'h5: r21 <= highblock0in;
         4'h6: r22 <= highblock0in;
         4'h7: r23 <= highblock0in;
         4'h8: r24 <= highblock0in;
         4'h9: r25 <= highblock0in;
         4'hA: r26 <= highblock0in;
         4'hB: r27 <= highblock0in;
         4'hC: r28 <= highblock0in;
         4'hD: r29 <= highblock0in;
         4'hE: r30 <= highblock0in;
         4'hF: r31 <= highblock0in;
      endcase
   end
end

// **************** Highblock1 ****************

reg [7:0]	r48, r49, r50, r51, r52, r53, r54, r55;
reg [7:0]	r56, r57, r58, r59, r60, r61, r62, r63;

// Read
always @(location or
		r48 or r49 or r50 or r51 or r52 or r53 or r54 or r55 or
		r56 or r57 or r58 or r59 or r60 or r61 or r62 or r63
) begin
   case (location[3:0])
      4'h0: highblock1out <= r48;
      4'h1: highblock1out <= r49;
      4'h2: highblock1out <= r50;
      4'h3: highblock1out <= r51;
      4'h4: highblock1out <= r52;
      4'h5: highblock1out <= r53;
      4'h6: highblock1out <= r54;
      4'h7: highblock1out <= r55;
      4'h8: highblock1out <= r56;
      4'h9: highblock1out <= r57;
      4'hA: highblock1out <= r58;
      4'hB: highblock1out <= r59;
      4'hC: highblock1out <= r60;
      4'hD: highblock1out <= r61;
      4'hE: highblock1out <= r62;
      4'hF: highblock1out <= r63;
   endcase
end

// Write
always @(posedge clk) begin
   if (we & highblock1sel) begin
      case (location[3:0])
         4'h0: r48 <= highblock1in;
         4'h1: r49 <= highblock1in;
         4'h2: r50 <= highblock1in;
         4'h3: r51 <= highblock1in;
         4'h4: r52 <= highblock1in;
         4'h5: r53 <= highblock1in;
         4'h6: r54 <= highblock1in;
         4'h7: r55 <= highblock1in;
         4'h8: r56 <= highblock1in;
         4'h9: r57 <= highblock1in;
         4'hA: r58 <= highblock1in;
         4'hB: r59 <= highblock1in;
         4'hC: r60 <= highblock1in;
         4'hD: r61 <= highblock1in;
         4'hE: r62 <= highblock1in;
         4'hF: r63 <= highblock1in;
      endcase
   end
end
      

// **************** Highblock2 ****************

reg [7:0]	r80, r81, r82, r83, r84, r85, r86, r87;
reg [7:0]	r88, r89, r90, r91, r92, r93, r94, r95;

// Read
always @(location or
		r80 or r81 or r82 or r83 or r84 or r85 or r86 or r87 or
		r88 or r89 or r90 or r91 or r92 or r93 or r94 or r95
) begin
   case (location[3:0])
      4'h0: highblock2out <= r80;
      4'h1: highblock2out <= r81;
      4'h2: highblock2out <= r82;
      4'h3: highblock2out <= r83;
      4'h4: highblock2out <= r84;
      4'h5: highblock2out <= r85;
      4'h6: highblock2out <= r86;
      4'h7: highblock2out <= r87;
      4'h8: highblock2out <= r88;
      4'h9: highblock2out <= r89;
      4'hA: highblock2out <= r90;
      4'hB: highblock2out <= r91;
      4'hC: highblock2out <= r92;
      4'hD: highblock2out <= r93;
      4'hE: highblock2out <= r94;
      4'hF: highblock2out <= r95;
   endcase
end

// Write
always @(posedge clk) begin
   if (we & highblock2sel) begin
      case (location[3:0])
         4'h0: r80 <= highblock2in;
         4'h1: r81 <= highblock2in;
         4'h2: r82 <= highblock2in;
         4'h3: r83 <= highblock2in;
         4'h4: r84 <= highblock2in;
         4'h5: r85 <= highblock2in;
         4'h6: r86 <= highblock2in;
         4'h7: r87 <= highblock2in;
         4'h8: r88 <= highblock2in;
         4'h9: r89 <= highblock2in;
         4'hA: r90 <= highblock2in;
         4'hB: r91 <= highblock2in;
         4'hC: r92 <= highblock2in;
         4'hD: r93 <= highblock2in;
         4'hE: r94 <= highblock2in;
         4'hF: r95 <= highblock2in;
      endcase
   end
end

// **************** Highblock3 ****************

// *** The Following Registers are removed because of CUSTOM Hardware (see piccpu.v) **
//
//    r129 (or 7E)
//
// **********
reg [7:0]	r112, r113, r114, r115, r116, r117, r118, r119;
reg [7:0]	r120, r121, r122, r123, r124, r125, r126 /*, r127*/ ;

// Read
always @(location or
		r112 or r113 or r114 or r115 or r116 or r117 or r118 or r119 or
		r120 or r121 or r122 or r123 or r124 or r125 or r126 /* or r127 */
) begin
   case (location[3:0])
      4'h0: highblock3out <= r112;
      4'h1: highblock3out <= r113;
      4'h2: highblock3out <= r114;
      4'h3: highblock3out <= r115;
      4'h4: highblock3out <= r116;
      4'h5: highblock3out <= r117;
      4'h6: highblock3out <= r118;
      4'h7: highblock3out <= r119;
      4'h8: highblock3out <= r120;
      4'h9: highblock3out <= r121;
      4'hA: highblock3out <= r122;
      4'hB: highblock3out <= r123;
      4'hC: highblock3out <= r124;
      4'hD: highblock3out <= r125;
      4'hE: highblock3out <= r126;
      4'hF: highblock3out <= 8'hff /* r127*/ ;
   endcase
end

// Write
always @(posedge clk) begin
   if (we & highblock3sel) begin
      case (location[3:0])
         4'h0: r112 <= highblock3in;
         4'h1: r113 <= highblock3in;
         4'h2: r114 <= highblock3in;
         4'h3: r115 <= highblock3in;
         4'h4: r116 <= highblock3in;
         4'h5: r117 <= highblock3in;
         4'h6: r118 <= highblock3in;
         4'h7: r119 <= highblock3in;
         4'h8: r120 <= highblock3in;
         4'h9: r121 <= highblock3in;
         4'hA: r122 <= highblock3in;
         4'hB: r123 <= highblock3in;
         4'hC: r124 <= highblock3in;
         4'hD: r125 <= highblock3in;
         4'hE: r126 <= highblock3in;
         4'hF: /* r127 <= highblock3in */;
      endcase
   end
end

// synopsys translate_off
`define CLEAR_MEMORY
`ifdef CLEAR_MEMORY
initial
begin
   $display ("Clearing SRAM.");
   clear_memory;
end
task clear_memory;
begin
   // Common registers
   r8  = 0;
   r9  = 0;
   r10 = 0;
   r11 = 0;
   r12 = 0;
   r13 = 0;
   r14 = 0;
   r15 = 0;

   // Bank #0
   r16 = 0;
   r17 = 0;
   r18 = 0;
   r19 = 0;
   r20 = 0;
   r21 = 0;
   r22 = 0;
   r23 = 0;
   r24 = 0;
   r25 = 0;
   r26 = 0;
   r27 = 0;
   r28 = 0;
   r29 = 0;
   r30 = 0;
   r31 = 0;

   // Bank #1
   r48 = 0;
   r49 = 0;
   r50 = 0;
   r51 = 0;
   r52 = 0;
   r53 = 0;
   r54 = 0;
   r55 = 0;
   r56 = 0;
   r57 = 0;
   r58 = 0;
   r59 = 0;
   r60 = 0;
   r61 = 0;
   r62 = 0;
   r63 = 0;

   // Bank #2