📄 mfrc500uc.lst
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492 * -o mask (IN)
493 * Bit mask to clear
494 * return: none
495 *
496 * This function performs a read - modify - write sequence
497 * on the specified register. All bits with a 1 in the mask
498 * are cleared - all other bits keep their original value.
499 */
500 void ClearBitMask(unsigned char reg,unsigned char mask);
501
502 /// Flush remaining data from the FIFO
503 /*!
504 * -o none
505 * return: none
506 *
507 * This function erases all remaining data in the MF RC 500's FIFO .
508 * Before writing new data or starting a new command, all remaining data
509 * from former commands should be deleted.
510 */
511 void FlushFIFO(void);
512
513 /// Sleep several milliseconds
514 /*
515 The implementation of this function depends heavily
516 on the microcontroller in use. The measurement need not to be
517 very accurate. Only make sure, that the periode is not shorter, than
518 the required one.
519 */
520 void SleepMs(unsigned short ms);
521
522 /// Sleep several microseconds
523 /*
524 The implementation of this function depends heavily
525 on the microcontroller in use. The measurement need not to be
526 very accurate. Only make sure, that the periode is not shorter, than
527 the required one.
528 */
529 void SleepUs(unsigned short us);
530
531
532 ///////////////////////////////////////////////////////////////////////
533 // M I F A R E M O D U L E C O N F I G U R A T I O N
534 ///////////////////////////////////////////////////////////////////////
535 char Mf500PcdConfig(void)
536 {
537 1 char status = MI_RESETERR;
538 1
539 1 status = PcdReset();
540 1
541 1 if (status == MI_OK)
542 1 {
543 2 if ((status = PcdBasicRegisterConfiguration()) == MI_OK);
544 2 {
545 3 Mf500PcdWriteAttrib(); // write current modulation parameters
546 3 PcdRfReset(1); // Rf - reset and enable output driver
547 3 }
548 2 }
549 1 return status;
550 1 }
551
C51 COMPILER V7.00 MFRC500UC 03/05/2004 15:25:52 PAGE 10
552 ///////////////////////////////////////////////////////////////////////
553 // M I F A R E R E M O T E A N T E N N A
554 // Configuration of slave module
555 ///////////////////////////////////////////////////////////////////////
556 char Mf500ActiveAntennaSlaveConfig(void)
557 {
558 1 char status = MI_OK;
559 1
560 1 FlushFIFO(); // empty FIFO
561 1 ResetInfo(MInfo);
562 1 MSndBuffer[0] = 0x10; // addr low byte
563 1 MSndBuffer[1] = 0x00; // addr high byte
564 1
565 1 MSndBuffer[2] = 0x00; // Page
566 1 MSndBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
567 1 MSndBuffer[4] = 0x3F; // RegCwConductance
568 1 MSndBuffer[5] = 0x3F; // RFU13
569 1 MSndBuffer[6] = 0x19; // RFU14
570 1 MSndBuffer[7] = 0x13; // RegModWidth
571 1 MSndBuffer[8] = 0x00; // RFU16
572 1 MSndBuffer[9] = 0x00; // RFU17
573 1
574 1 MSndBuffer[10] = 0x00; // Page
575 1 MSndBuffer[11] = 0x73; // RegRxControl1
576 1 MSndBuffer[12] = 0x08; // RegDecoderControl
577 1 MSndBuffer[13] = 0x6c; // RegBitPhase
578 1 MSndBuffer[14] = 0xFF; // RegRxThreshold
579 1 MSndBuffer[15] = 0x00; // RegBPSKDemControl
580 1 MSndBuffer[16] = 0x00; // RegRxControl2
581 1 MSndBuffer[17] = 0x00; // RegClockQControl
582 1
583 1 MSndBuffer[18] = 0x00; // Page
584 1 MSndBuffer[19] = 0x06; // RegRxWait
585 1 MSndBuffer[20] = 0x03; // RegChannelRedundancy
586 1 MSndBuffer[21] = 0x63; // RegCRCPresetLSB
587 1 MSndBuffer[22] = 0x63; // RegCRCPresetMSB
588 1 MSndBuffer[23] = 0x0; // RFU25
589 1 MSndBuffer[24] = 0x04; // RegMfOutSelect enable mfout = manchester HT
590 1 MSndBuffer[25] = 0x00; // RFU27
591 1
592 1 // PAGE 5 FIFO, Timer and IRQ-Pin Configuration
593 1 MSndBuffer[26] = 0x00; // Page
594 1 MSndBuffer[27] = 0x08; // RegFIFOLevel
595 1 MSndBuffer[28] = 0x07; // RegTimerClock
596 1 MSndBuffer[29] = 0x06; // RegTimerControl
597 1 MSndBuffer[30] = 0x0A; // RegTimerReload
598 1 MSndBuffer[31] = 0x02; // RegIRqPinConfig
599 1 MSndBuffer[32] = 0x00; // RFU
600 1 MSndBuffer[33] = 0x00; // RFU
601 1 MInfo.nBytesToSend = 34;
602 1
603 1 status = PcdSingleResponseCmd(PCD_WRITEE2,
604 1 MSndBuffer,
605 1 MRcvBuffer,
606 1 &MInfo); // write e2
607 1 return status;
608 1 }
609
610 ///////////////////////////////////////////////////////////////////////
611 // M I F A R E R E M O T E A N T E N N A
612 // Configuration of master module
613 ///////////////////////////////////////////////////////////////////////
C51 COMPILER V7.00 MFRC500UC 03/05/2004 15:25:52 PAGE 11
614 char Mf500ActiveAntennaMasterConfig(void)
615 {
616 1 char status = MI_OK;
617 1
618 1 WriteRC(RegRxControl2,0x42);
619 1 WriteRC(RegTxControl,0x10);
620 1 WriteRC(RegBitPhase,0x11);
621 1 WriteRC(RegMfOutSelect,0x02);
622 1
623 1 return status;
624 1 }
625
626 ///////////////////////////////////////////////////////////////////////
627 // M I F A R E R E Q U E S T
628 ///////////////////////////////////////////////////////////////////////
629 char Mf500PiccRequest(unsigned char req_code, // request code ALL = 0x52
630 // or IDLE = 0x26
631 unsigned char *atq) // answer to request
632 {
633 1 return Mf500PiccCommonRequest(req_code,atq);
634 1 }
635
636 ///////////////////////////////////////////////////////////////////////
637 // M I F A R E C O M M O N R E Q U E S T
638 ///////////////////////////////////////////////////////////////////////
639 char Mf500PiccCommonRequest(unsigned char req_code,
640 unsigned char *atq)
641 {
642 1 char status = MI_OK;
643 1
644 1 //************* initialize ******************************
645 1 if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
646 1 {
647 2
648 2 PcdSetTmo(60);
649 2
650 2 WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
651 2 ClearBitMask(RegControl,0x08); // disable crypto 1 unit
652 2 WriteRC(RegBitFraming,0x07); // set TxLastBits to 7
653 2
654 2 ResetInfo(MInfo);
655 2 MSndBuffer[0] = req_code;
656 2 MInfo.nBytesToSend = 1;
657 2 MInfo.DisableDF = 1;
658 2 status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
659 2 MSndBuffer,
660 2 MRcvBuffer,
661 2 &MInfo);
662 2 if ((status == MI_OK) && (MInfo.nBitsReceived != 16)) // 2 bytes expected
663 2 {
664 3 status = MI_BITCOUNTERR;
665 3 }
666 2 if ((status == MI_COLLERR) && (MInfo.nBitsReceived == 16)) //
667 2 status = MI_OK; // all received tag-types are combined to the 16 bit
668 2
669 2 // in any case, copy received data to output - for debugging reasons
670 2 if (MInfo.nBytesReceived >= 2)
671 2 {
672 3 memcpy(atq,MRcvBuffer,2);
673 3 }
674 2 else
675 2 {
C51 COMPILER V7.00 MFRC500UC 03/05/2004 15:25:52 PAGE 12
676 3 if (MInfo.nBytesReceived == 1)
677 3 atq[0] = MRcvBuffer[0];
678 3 else
679 3 atq[0] = 0x00;
680 3 atq[1] = 0x00;
681 3 }
682 2 }
683 1 return status;
684 1 }
685
686 ///////////////////////////////////////////////////////////////////////
687 // M I F A R E A N T I C O L L I S I O N
688 // for standard select
689 ///////////////////////////////////////////////////////////////////////
690 char Mf500PiccAnticoll (unsigned char bcnt,
691 unsigned char *snr)
692 {
693 1 return Mf500PiccCascAnticoll(0x93,bcnt,snr); // first cascade level
694 1 }
695
696 ///////////////////////////////////////////////////////////////////////
697 // M I F A R E A N T I C O L L I S I O N
698 // for extended serial numbers
699 ///////////////////////////////////////////////////////////////////////
700 char Mf500PiccCascAnticoll (unsigned char select_code,
701 unsigned char bcnt,
702 unsigned char *snr)
703 {
704 1 char status = MI_OK;
705 1 char snr_in[4]; // copy of the input parameter snr
706 1 char nbytes = 0; // how many bytes received
707 1 char nbits = 0; // how many bits received
708 1 char complete = 0; // complete snr recived
709 1 short i = 0;
710 1 char byteOffset = 0;
711 1 unsigned char snr_crc; // check byte calculation
712 1 unsigned char snr_check;
713 1 unsigned char dummyShift1; // dummy byte for snr shift
714 1 unsigned char dummyShift2; // dummy byte for snr shift
715 1
716 1 //************* Initialisierung ******************************
717 1 if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
718 1 {
719 2 PcdSetTmo(106);
720 2
721 2 memcpy(snr_in,snr,4);
722 2
723 2 WriteRC(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
724 2 ClearBitMask(RegControl,0x08); // disable crypto 1 unit
725 2
726 2 //************** Anticollision Loop ***************************
727 2 complete=0;
728 2 while (!complete && (status == MI_OK) )
729 2 {
730 3 // if there is a communication problem on the RF interface, bcnt
731 3 // could be larger than 32 - folowing loops will be defective.
732 3 if (bcnt > 32)
733 3 {
734 4 status = MI_WRONG_PARAMETER_VALUE;
735 4 continue;
736 4 }
737 3 ResetInfo(MInfo);
C51 COMPILER V7.00 MFRC500UC 03/05/2004 15:25:52 PAGE 13
738 3 MInfo.cmd = select_code; // pass command flag to ISR
739 3 MInfo.DisableDF = 1;
740 3 WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
741 3 nbits = bcnt % 8; // remaining number of bits
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