risc8.cfg

RISC的指令VerilogHDL实现

# Virsim Configuration File
version "2.2.0"

# Files Open:
#   Designator  Sources  Filename
#   ----------  -------  --------
#       V1         y     /apps/arvind/java/risc8/sim/vcdplus.vpd

define exprgroup AutoExprGroup0;

define linkwindow A
	time 2615 "1 s",
	exprgroup "AutoExprGroup0";

define linkwindow SIM
	time 705 "1 s",
	exprgroup "AutoExprGroup0";

define radix command "Verilog"
	add "4'h0" "add",
	add "4'h1" "and",
	add "4'h2" "or",
	add "4'h3" "xor",
	add "4'h4" "not",
	add "4'h5" "shl",
	add "4'h6" "shr",
	add "4'h7" "asr",
	add "4'h8" "tha",
	add "4'h9" "thb";

define radix op "Verilog"
	add "8'b00000???" "add",
	add "8'b00001???" "adc",
	add "8'b00010???" "sub",
	add "8'b00011???" "sbc",
	add "8'b00100???" "inc",
	add "8'b00101???" "dec",
	add "8'b00110???" "cmp",
	add "8'b00111???" "subr",
	add "8'b01000???" "and",
	add "8'b01001???" "or",
	add "8'b01010???" "xor",
	add "8'b01011???" "not",
	add "8'b01100???" "shl",
	add "8'b01101???" "shr",
	add "8'b01110???" "udiv",
	add "8'b01111000" "wrps",
	add "8'b01111001" "rdps",
	add "8'b01111010" "nop",
	add "8'b01111011" "nop1",
	add "8'b011111??" "nop2",
	add "8'b10000???" "mov ro rn",
	add "8'b10001???" "mov rn r0",
	add "8'b10010???" "psh",
	add "8'b10011???" "pop",
	add "8'b101000??" "ldr",
	add "8'b101001??" "str",
	add "8'b101010??" "mov sp an",
	add "8'b101011??" "mov an sp",
	add "8'b101100??" "inca",
	add "8'b101101??" "deca",
	add "8'b101110??" "jmpAn",
	add "8'b10111100" "ret",
	add "8'b10111101" "ror",
	add "8'b10111110" "rorc",
	add "8'b10111111" "asr",
	add "8'b11000???" "umul",
	add "8'b110010??" "ldo",
	add "8'b110011??" "sto",
	add "8'b11010???" "ldi",
	add "8'b11011???" "jmpr",
	add "8'b11100???" "jmpa",
	add "8'b11101???" "jmps",
	add "8'b11110???" "lda",
	add "8'b11111???" "sta";

define group AutoGroup0
	add "V1" "main.U0.clk" strength 1 ,
	add "V1" "main.U0.rst_n" strength 1 ,
	add "V1" "main.U0.cycle" strength 1 ,
	add "V1" "main.U0.write" strength 1 ,
	add "V1" "main.U0.address" hex 1 ,
	add "V1" "main.U0.ifetch" strength 1 ,
	add "V1" "main.U0.data_in" hex 1 ,
	add "V1" "main.U0.data_out" hex 1 ,
	add "V1" "main.U0.ready" strength 1 ,
	add "V1" "main.U0.iack" strength 1 ,
	add "V1" "main.U0.U_regb_biu.int_type" hex 1 ,
	add "V1" "main.U0.ie" strength 1 ,
	add "V1" "main.U0.int" strength 1 ,
	add "V1" "main.U0.nmi" strength 1 ,
	add "V1" "main.U0.U_control.div_reg" strength 1 ,
	add "V1" "main.U0.U_control.int_reg" strength 1 ,
	add "V1" "main.U0.U_control.nmi_reg" strength 1 ,
	add "V1" "main.U0.U_regb_biu.bus_state" hex 1 ,
	add "V1" "main.U0.scan_en" strength 1 ,
	add "V1" "main.U0.scan_in" strength 1 ,
	add "V1" "main.U0.U_alu.mul" strength 1 ,
	add "V1" "main.U0.U_alu.div" strength 1 ,
	add "V1" "main.U0.U_regb_biu.address_save" hex 1 ,
	add "V1" "main.U0.U_regb_biu.clear_queue" strength 1 ,
	add "V1" "main.U0.U_regb_biu.stop_fetch" strength 1 ,
	add "V1" "main.U0.U_regb_biu.addr_op" hex 1 ,
	add "V1" "main.U0.U_regb_biu.data_access" strength 1 ,
	add "V1" "main.U0.U_regb_biu.data_access_next" strength 1 ,
	add "V1" "main.U0.U_alu.div_restore" strength 1 ,
	add "V1" "main.U0.U_alu.muldiv_init" strength 1 ,
	add "V1" "main.U0.U_alu.muldiv_save0" strength 1 ,
	add "V1" "main.U0.U_alu.muldiv_save1" strength 1 ,
	add "V1" "main.U0.U_regb_biu.sp" hex 1 ,
	add "V1" "main.U0.scan_out" strength 1 ,
	add "V1" "main.U0.U_control.state" hex 1 ,
	add "V1" "main.U0.U_control.data_ready" strength 1 ,
	add "V1" "main.U0.U_control.condition" strength 1 ,
	add "V1" "main.U0.U_control.load_opcode_tmp" strength 1 ,
	add "V1" "main.U0.U_control.sel_opcode_tmp" strength 1 ,
	add "V1" "main.U0.U_control.psw" hex 1 ,
	add "V1" "main.U0.U_control.opcode_op" hex 1 ,
	add "V1" "main.U0.U_control.opcode" op 1 ,
	add "V1" "main.U0.U_control.opcode" hex 1 ,
	add "V1" "main.U0.U_control.opcode_op" hex 1 ,
	add "V1" "main.U0.U_control.opcode_valid" strength 1 ,
	add "V1" "main.U0.U_control.queue_out" hex 1 ,
	add "V1" "main.U0.U_control.state" hex 1 ,
	add "V1" "main.U0.U_control.decode" hex 1 ,
	add "V1" "main.U0.U_alu.alu_cmd" hex 1 ,
	add "V1" "main.U0.alu_cmd" command 1 ,
	add "V1" "main.U0.a_addr" hex 1 ,
	add "V1" "main.U0.b_addr" hex 1 ,
	add "V1" "main.U0.w_addr" hex 1 ,
	add "V1" "main.U0.U_regb_biu.pc" hex 1 ,
	add "V1" "main.U0.U_alu.a_lu" hex 1 ,
	add "V1" "main.U0.U_alu.b_lu" hex 1 ,
	add "V1" "main.U0.U_alu.a_adder" hex 1 ,
	add "V1" "main.U0.U_alu.b_adder" hex 1 ,
	add "V1" "main.U0.a_data" hex 1 ,
	add "V1" "main.U0.b_data" hex 1 ,
	add "V1" "main.U0.U_alu.a_alu" hex 1 ,
	add "V1" "main.U0.U_alu.b_alu" hex 1 ,
	add "V1" "main.U0.U_alu.a_reg" hex 1 ,
	add "V1" "main.U0.U_alu.p_reg" hex 1 ,
	add "V1" "main.U0.U_alu.carry_in" strength 1 ,
	add "V1" "main.U0.U_control.queue_count_gt0" strength 1 ,
	add "V1" "main.U0.U_control.queue_count_gt1" strength 1 ,
	add "V1" "main.U0.alu_out" hex 1 ,
	add "V1" "main.U0.U_regb_biu.w_data" hex 1 ,
	add "V1" "main.U0.U_control.data_op" hex 1 ,
	add "V1" "main.U0.U_control.addr_op" hex 1 ,
	add "V1" "main.U0.U_alu.a_src" hex 1 ,
	add "V1" "main.U0.U_alu.b_src" hex 1 ,
	add "V1" "main.U0.wr_reg" strength 1 ,
	add "V1" "main.U0.carry_src" hex 1 ,
	add "V1" "main.U0.U_alu.psw" hex 1 ,
	add "V1" "main.U0.invert_b" strength 1 ,
	add "V1" "main.U0.U_regb_biu.in_pointer" hex 1 ,
	add "V1" "main.U0.U_regb_biu.out_pointer" hex 1 ,
	add "V1" "main.U0.U_regb_biu.ready" strength 1 ,
	add "V1" "main.U0.U_regb_biu.read_opcode" strength 1 ,
	add "V1" "main.U0.U_regb_biu.queue_count" hex 1 ;

define hierarchy
	xposition 365,
	yposition 50,
	width 555,
	height 498,
	designator "V1",
	layout "default",
	topscope "main",
	pane1 199,
	focusscope "main.U0.U_regb_biu",
	pane2 268,
	locate "scopes",
	find "current",
	findtext "*",
	pane3 271,
	signals on,
	ports on,
	filtertext "*",
	signalscope "main.U0.U_regb_biu";

define wave
	xposition 20,
	yposition 140,
	width 968,
	height 608,
	linkwindow A,
	displayinfo 2668 "1 s" ppt 4 0,
	group "AutoGroup0",
	pane1 120,
	pane2 61;