risc8.ps

RISC的指令VerilogHDL实现

        /mis width string def
        /kis width string def
        /cf currentfile def 
        width height 8 [width 0 0 height neg 0 height] 
        { cf is readhexstring pop 
          cf mis readhexstring pop 
          cf yis readhexstring pop 
          cf kis readhexstring pop width cgray}  image
        bitmapsave restore 
        grestore
        } bind def
/BITMAPGRAY { 
	8 {fakecolorsetup} COMMONBITMAP
	} bind def
/BITMAPGRAYc { 
	8 {fakecolorsetup} COMMONBITMAPc
	} bind def
/ENDBITMAP {
	} bind def
end 
	/ALDmatrix matrix def ALDmatrix currentmatrix pop
/StartALD {
	/ALDsave save def
	 savematrix
	 ALDmatrix setmatrix
	} bind def
/InALD {
	 restorematrix
	} bind def
/DoneALD {
	 ALDsave restore
	} bind def
/I { setdash } bind def
/J { [] 0 setdash } bind def
%%EndProlog
%%BeginSetup
(5.5) FMVERSION
1 1 0 0 612 792 0 1 20 FMDOCUMENT
%%IncludeFont: Helvetica
0 0 /Helvetica FMFONTDEFINE
%%IncludeFont: Helvetica-Bold
1 0 /Helvetica-Bold FMFONTDEFINE
%%IncludeFont: Helvetica-Oblique
2 0 /Helvetica-Oblique FMFONTDEFINE
%%IncludeFont: Helvetica-BoldOblique
3 0 /Helvetica-BoldOblique FMFONTDEFINE
32 FMFILLS
0 0 FMFILL
1 0.1 FMFILL
2 0.3 FMFILL
3 0.5 FMFILL
4 0.7 FMFILL
5 0.9 FMFILL
6 0.97 FMFILL
7 1 FMFILL
8 <0f1e3c78f0e1c387> FMFILL
9 <0f87c3e1f0783c1e> FMFILL
10 <cccccccccccccccc> FMFILL
11 <ffff0000ffff0000> FMFILL
12 <8142241818244281> FMFILL
13 <03060c183060c081> FMFILL
14 <8040201008040201> FMFILL
16 1 FMFILL
17 0.9 FMFILL
18 0.7 FMFILL
19 0.5 FMFILL
20 0.3 FMFILL
21 0.1 FMFILL
22 0.03 FMFILL
23 0 FMFILL
24 <f0e1c3870f1e3c78> FMFILL
25 <f0783c1e0f87c3e1> FMFILL
26 <3333333333333333> FMFILL
27 <0000ffff0000ffff> FMFILL
28 <7ebddbe7e7dbbd7e> FMFILL
29 <fcf9f3e7cf9f3f7e> FMFILL
30 <7fbfdfeff7fbfdfe> FMFILL
%%EndSetup
%%Page: "1" 1
%%BeginPaperSize: Letter
%%EndPaperSize
612 792 0 FMBEGINPAGE
0 FrameSetSepColors
[
/Creator (FrameMaker 5.5.6.)
/Title (risc8)
/CreationDate (D:19990921114537)
/ModDate (D:20000207173903)
/DOCINFO FmPD2
FrameNoSep
0 0 0 1 0 0 0 1 K
J
-36 -45 648 837 C
0 0 0 1 0 0 0 1 K
-32.69 -8.79 605.14 45.21 R
7 X
V
63 72 567 72 2 L
V
1 H
2 Z
0 X
N
450.97 45 567 63.5 R
7 X
V
0 10 Q
0 X
(Page 2-1) 526.42 56.83 T
63 81 567 747 R
6 X
V
0.5 H
0 X
N
1 24 Q
-1.2 (8-bit RISC Microprocessor Core) 222.26 701 S
189 333 567 558 C
189 333 567 558 R
3 X
V
0 0 0 1 0 0 0 1 K
1 62 Q
0 X
(RISC8) 278.69 460.87 T
1 24 Q
(Doc. Re) 279 423 T
(vision 1.0) 367.99 423 T
(Core Re) 279 396 T
(vision 1.0) 370.66 396 T
(02/06/00 - S.Ara) 279 369 T
(vindhan) 456.07 369 T
-36 -45 648 837 C
0 0 0 1 0 0 0 1 K
FMENDPAGE
%%EndPage: "1" 1
%%Page: "2" 2
612 792 0 FMBEGINPAGE
0 FrameSetSepColors
FrameNoSep
-36 -45 648 837 C
0 0 0 1 0 0 0 1 K
-32.69 -8.79 605.14 45.21 R
7 X
V
1 20 Q
0 X
-1 (8-bit RISC Microprocessor Core) 45 738.17 S
549 720 45.59 720 2 L
1 H
2 Z
N
48.5 43.5 189 63 R
7 X
V
0 10 Q
0 X
(Page 2-2) 48.5 56.33 T
45.63 72 549 72 2 L
7 X
V
0 X
N
1 14 Q
(2.1) 45 701.67 T
(Pr) 81 701.67 T
(ocessor Features) 95.5 701.67 T
0 10 Q
(\245) 99 683.33 T
(Single clock Synchronous 8-bit load/store Risc Processor) 117 683.33 T
(\245) 99 669.33 T
(Most instructions are 1-byte in length and execute in 1 clock) 117 669.33 T
(\245) 99 655.33 T
(Synthesizable Soft core) 117 655.33 T
(-) 117 641.33 T
(Fast Compile time) 135 641.33 T
(-) 117 627.33 T
(As) 135 627.33 T
(small) 149.18 627.33 T
(as) 175.03 627.33 T
(3000) 188.1 627.33 T
(nand) 212.85 627.33 T
(gate) 237.61 627.33 T
(equivalent) 259.58 627.33 T
(\050including) 307.67 627.33 T
(register) 352.98 627.33 T
(bank\051) 388.83 627.33 T
(and) 416.36 627.33 T
(as) 435.55 627.33 T
(fast) 448.62 627.33 T
(as) 467.26 627.33 T
(300) 480.33 627.33 T
(MHz) 499.52 627.33 T
(using) 522.59 627.33 T
(0.25u technology.) 135 616.33 T
(\245) 99 602.33 T
(100% test coverage) 117 602.33 T
(\245) 99 588.33 T
(static) 117 588.33 T
(\245) 99 574.33 T
(Power Optimization centric RTL Code) 117 574.33 T
(\245) 99 560.33 T
(External Power Saving modes \050GATE clock, STOP clock, DIVIDE clock\051) 117 560.33 T
(\245) 99 546.33 T
(Power Compiler Friendly) 117 546.33 T
(\245) 99 532.33 T
(Perl bases assembler) 117 532.33 T
1 12 Q
(2.1.1) 45 510 T
(RISC8 Micr) 81 510 T
(opr) 144.11 510 T
(ocessor core) 163.2 510 T
(2.1.1.1) 81 487 T
(Description) 127.8 487 T
0 10 Q
(The RISC8 is a 8-bit, 3-stage pipelined load/store RISC microprocessor core) 81 470.33 T
(. Due to it\325) 419.3 470.33 T
(s simpler RISC) 463.82 470.33 T
(architecture it is v) 81 458.33 T
(er) 158.55 458.33 T
(y small in siz) 167.74 458.33 T
(e \050could be synthesiz) 224.26 458.33 T
(ed into 3000 nand equiv) 318.04 458.33 T
(alent gates\051 and also it can) 424.53 458.33 T
(be) 81 446.33 T
(synthesiz) 94.35 446.33 T
(ed) 135.88 446.33 T
(as) 149.22 446.33 T
(f) 162.01 446.33 T
(ast) 164.49 446.33 T
(as) 180.05 446.33 T
(300) 192.84 446.33 T
(MHz) 211.74 446.33 T
(using) 234.51 446.33 T
(0.25u) 260.64 446.33 T
(technology) 287.89 446.33 T
(.) 335.24 446.33 T
(Most) 340.25 446.33 T
(of) 364.14 446.33 T
(the) 374.71 446.33 T
(instr) 390.83 446.33 T
(uctions) 409.87 446.33 T
(,) 441.4 446.33 T
(e) 446.41 446.33 T
(xcept) 451.67 446.33 T
(a) 477.79 446.33 T
(f) 485.58 446.33 T
(e) 488.06 446.33 T
(w) 493.42 446.33 T
(load/store) 502.86 446.33 T
(instr) 81 434.33 T
(uctions) 100.04 434.33 T
(and) 133.87 434.33 T
(jump) 152.7 434.33 T
(are) 176.51 434.33 T
(in) 193.11 434.33 T
(8-bit) 203.04 434.33 T
(in) 224.63 434.33 T
(length) 234.56 434.33 T
(to) 263.95 434.33 T
(pro) 274.44 434.33 T
(vide) 288.74 434.33 T
(a) 309.22 434.33 T
(compact) 316.93 434.33 T
(code) 356.87 434.33 T
(.) 378.4 434.33 T
(F) 383.33 434.33 T
(or) 389.14 434.33 T
(simplicity) 400.17 434.33 T
(,) 439.72 434.33 T
(the) 444.65 434.33 T
(instr) 460.7 434.33 T
(uction) 479.74 434.33 T
(and) 508.57 434.33 T
(data) 527.39 434.33 T
(f) 81 422.33 T
(etch share the same b) 83.48 422.33 T
(us) 182.22 422.33 T
(.) 192.63 422.33 T
(RISC8 Module Hierarchy:) 81 398.33 T
(- risc8) 117 381.33 T
(- risc8_alu) 135 367.33 T
(- risc8_regb_biu) 135 353.33 T
(- risc8_control) 135 339.33 T
(The core mainly consists of 3 b) 81 310.33 T
(loc) 218.63 310.33 T
(ks) 231.21 310.33 T
(, namely the control, alu and registerbank-b) 241.06 310.33 T
(us interf) 433.17 310.33 T
(ace units) 468.44 310.33 T
(.) 508.31 310.33 T
1 F
(Contr) 99 286.33 T
(ol unit \050contr) 125.46 286.33 T
(ol\051) 186.37 286.33 T
0 F
(The control unit is the main unit of the core. It decodes the opcodes and controls the alu and register) 99 271.33 T
(bank operations. It also services the interrupts and works with the BIU to handle instruction/data) 99 260.33 T
(fetches.) 99 249.33 T
1 F
(Arithmetic Logic unit \050alu\051) 99 234.33 T
0 F
(The ALU contains the adder, subtracter, shifter, multiplier, divider and the logical operation units. The) 99 219.33 T
(adder/subtracter) 99 208.33 T
(is) 174.49 208.33 T
(implemented) 184.39 208.33 T
(in) 244.31 208.33 T
(DesignWare,) 254.77 208.33 T
(so) 315.24 208.33 T
(that) 328.48 208.33 T
(the) 347.84 208.33 T
(design_compiler) 364.42 208.33 T
(can) 439.9 208.33 T
(pick) 458.7 208.33 T
(the) 479.16 208.33 T
(appropriate) 495.74 208.33 T
(implementation according to speed and area criteria.) 99 197.33 T
139 182.33 99 182.33 2 L
0.5 H
0 Z
N
2 F
(multiplier) 99 183.33 T
0 F
(The) 99 169.33 T
(multiplier) 118.51 169.33 T
(is) 160.78 169.33 T
(an) 170.28 169.33 T
(one) 183.67 169.33 T
(bit) 202.63 169.33 T
(per) 215.46 169.33 T
(cycle) 232.19 169.33 T
(unsigned) 257.24 169.33 T
(multiplier.) 300.1 169.33 T
(It) 345.15 169.33 T
(multiplies) 352.99 169.33 T
(2,) 396.94 169.33 T
(8-bit) 407.55 169.33 T
(operands) 429.28 169.33 T
(and) 473.24 169.33 T
(produces) 492.2 169.33 T
(an) 535.6 169.33 T
(16-bit product. The multiplication takes totally 11 clocks. First cycle for initialization, 8 clocks for the) 99 158.33 T
(multiplication and 2 additional clocks for writing back the 16-bit product.) 99 147.33 T
(The multiplier has a 2, 8-bit registers P_reg and A_reg. Here is the multiplier algorithm:) 99 133.33 T
(0. The P_reg is initialized with 0 and the A_reg is loaded with the multiplicand A.) 99 119.33 T
(1. If the least significant bit of A_reg is "1" then add the multiplier operand "B" to the P_reg. otherwise) 99 105.33 T
(add "00" to P_reg.) 99 94.33 T
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612 792 0 FMBEGINPAGE
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FrameNoSep
-36 -45 648 837 C
0 0 0 1 0 0 0 1 K
-32.69 -8.79 605.14 45.21 R
7 X
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1 20 Q
0 X
-1 (8-bit RISC Microprocessor Core) 294.71 738.17 S
567 720 63 720 2 L
1 H
2 Z
N
63 72 567 72 2 L
N
442.5 45 567 64.5 R
7 X
V
0 10 Q
0 X
(Page 2-3) 526.42 57.83 T
(2.) 117 704.33 T
(Shift) 127.73 704.33 T
(right) 150.13 704.33 T
(P_reg) 171.96 704.33 T
(and) 201.03 704.33 T
(A_reg,) 220.1 704.33 T
(with) 251.95 704.33 T
(the) 272.12 704.33 T
(carry) 288.41 704.33 T
(from) 313.02 704.33 T
(the) 335.4 704.33 T
(previous) 351.69 704.33 T
(add) 391.87 704.33 T
(being) 410.94 704.33 T
(moved) 437.79 704.33 T
(to) 470.19 704.33 T
(the) 480.91 704.33 T
(higher-order) 497.2 704.33 T
(bit) 554.05 704.33 T
(of P_reg and the lower-order bit of P_reg moved into the higher-order bit of A_reg.) 117 693.33 T
(3.) 117 679.33 T
(Continue) 127.92 679.33 T
(the) 170.53 679.33 T
(steps) 187.01 679.33 T
(1) 213.49 679.33 T
(and) 221.64 679.33 T
(2) 240.9 679.33 T
(for) 249.05 679.33 T
(8-times.) 263.3 679.33 T
(Now) 301.44 679.33 T
(the) 324.03 679.33 T
(P_reg) 340.51 679.33 T
(will) 369.77 679.33 T
(have) 386.24 679.33 T
(the) 410.5 679.33 T
(higher) 426.99 679.33 T
(8-bits) 457.36 679.33 T
(of) 484.39 679.33 T
(the) 495.32 679.33 T
(product) 511.8 679.33 T
(and) 547.74 679.33 T
(A_reg will have the lower 8-bits of the product.) 117 668.33 T
148.11 410.33 117 410.33 2 L
0.5 H
0 Z
N
2 F
(Divider) 117 411.33 T
0 F
(The) 117 397.33 T
(Division) 136.92 397.33 T
(algorithm) 174.61 397.33 T
(is) 218.42 397.33 T
(similar) 228.33 397.33 T
(to) 259.9 397.33 T
(the) 270.93 397.33 T
(multiplication.) 287.52 397.33 T
(It) 350.78 397.33 T
(is) 359.02 397.33 T
(a) 368.93 397.33 T
(1-bit) 377.18 397.33 T
(per) 399.32 397.33 T
(cycle) 416.46 397.33 T
(divider.) 441.93 397.33 T
(It) 476.85 397.33 T
(takes) 485.1 397.33 T
(12) 511.69 397.33 T
(clocks) 525.5 397.33 T
(to) 555.97 397.33 T
(complete a division. First clock for the initialization, 8 clocks for the division, 1 clock for the restore) 117 386.33 T
(operation) 117 375.33 T
(and) 160.9 375.33 T
(2) 179.79 375.33 T
(additional) 187.57 375.33 T
(clock) 232.58 375.33 T
(to) 257.57 375.33 T
(write) 268.12 375.33 T
(back) 291.44 375.33 T
(the) 314.77 375.33 T
(8-bit) 330.89 375.33 T
(quotient) 352.55 375.33 T
(and) 390.34 375.33 T
(the) 409.23 375.33 T
(8-bit) 425.34 375.33 T
(remainder.) 447 375.33 T
(The) 497 375.33 T
(divider) 516.45 375.33 T
(and) 548.11 375.33 T
(the multiplier share the same P_reg and A_reg registers. Here is the divider algorithm:) 117 364.33 T
(0.) 117 350.33 T
(Initialize) 127.89 350.33 T
(P_reg) 166.55 350.33 T
(with) 195.78 350.33 T
("00") 216.11 350.33 T
(and) 236.87 350.33 T
(A_reg) 256.1 350.33 T
(with) 285.33 350.33 T
(dividend) 305.65 350.33 T
("A".) 345.44 350.33 T
(Please) 364.54 350.33 T
(note) 397.65 350.33 T
(P) 419.66 350.33 T
(and) 428.88 350.33 T
(B) 448.11 350.33 T
(are) 457.32 350.33 T
(zero) 474.32 350.33 T
(extend) 496.32 350.33 T
(to) 528.88 350.33 T
(9-bits.) 539.77 350.33 T
(1. if P_reg is negative, shift {P_reg, A_reg} one bit left, add divisor operand "B" to P_reg) 117 336.33 T
(else if P_reg is positive, shift {P_reg, A_reg} one bit left, subtract divisor operand "B" from P_reg) 117 322.33 T
(2. if P is negative, set low-order bit of A_reg to "0" else to "1".) 117 308.33 T
(3. Iterate steps 1 and 2, 8 times) 117 294.33 T
(4. If P_reg is negative add "B" to P_reg else add "00") 117 280.33 T
(Now P_reg contains the remainder and A_reg contains the quotient.) 117 266.33 T
99 436 567 651 C
99 436 567 651 R
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0 0 0 1 0 0 0 1 K
396 570 522 597 R
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234 570 359 597 R
N
384.96 579 384.96 581.64 394.19 579 384.96 576.36 4 Y
1 H
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384.96 579 384.96 581.64 394.19 579 384.96 576.36 4 Y
V
360 579 384.46 579 2 L
0.5 H
2 Z
N
162 525 234 525 216 507 180 507 4 Y
N
117 597 189 597 171 579 135 579 4 Y
N
90 450 1.5 1.5 270 135 617.19 GG
135 616.69 140.12 616.69 135 598.81 129.88 616.69 4 Y
1 H
0 Z
N
135 616.69 140.12 616.69 135 598.81 129.88 616.69 4 Y
V
135 624 135 617.19 2 L
3 H
2 Z
N
90 450 1.5 1.5 270 171 617.19 GG
171 616.69 176.12 616.69 171 598.81 165.88 616.69 4 Y
1 H
0 Z
N
171 616.69 176.12 616.69 171 598.81 165.88 616.69 4 Y
V
171 624 171 617.19 2 L
3 H
2 Z
N
90 450 1.5 1.5 270 180 545.19