counter1000.vhd

用VHDL语言编写

--1000进制计数器
--
--端口说明
	--clk_in	: 输入脉冲
	--clk_out	: 输出脉冲
--999 = B"1111100111"

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter1000 IS
	PORT(
		clk_in			: IN	STD_LOGIC;
		clk_out			: OUT	STD_LOGIC);
END counter1000;

ARCHITECTURE counter1000_run OF counter1000 IS
	SIGNAL mid	: STD_LOGIC_VECTOR(9 downto 0);
BEGIN
	PROCESS (clk_in)
	BEGIN
		IF (clk_in'EVENT AND clk_in = '1') THEN
			IF mid = "1111100111" THEN
			    mid <= "0000000000";
			ELSE
			    mid <= mid+'1';
			END IF;
		END IF;
	END PROCESS;
	
	clk_out <= mid(9) AND mid(8) AND mid(7) AND mid(6)
			   AND mid(5) AND (NOT mid(4)) AND (NOT mid(3))
			   AND mid(2) AND mid(1) AND mid(0);
END counter1000_run;