860qmc.h

MPC860初始化QMC在HDLC模式示例

/*-----------------------------------------------------------------------				
*
* File:  860QMC.h
*
* Description:  
*
* 		Constants and Definitions for MPC860 QMC Example.
*     [Interrupt-driven version].
*
* History:
*
* 12 JUN 96    saw     Initial version.
* 20 FEB 97    sgj     Created HDLC version from IRDa version
* 26 AUG 97    sgj     Modified BD structure and cleaned up
* 20 NOV 97    jay     Modified BD structure and cleaned up
* 07 JAN 98	   ecg	  Created Transparent Version from HDLC version
* 22 JAN 98    ecg     Created Ethernet version from Transparent version
* 20 FEB 98		ggh/	  Created QMC version from Ethernet version
*					ecg
*-----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
/*                   MPC8xx CONSTANTS AND DEFINITIONS                   */
/*----------------------------------------------------------------------*/

#define INTERRUPT_LEVEL 4     /* integer between 0 and 7 inclusive */
#define BASE_EVT 0x0          /* Base Address of Exception Vector Table */
#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  /* Base address of external 
											               interrupt code */
#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)


/*----------------------------------------------------------------------*/
/*                APPLICATION CONSTANTS AND DEFINITIONS                 */
/*----------------------------------------------------------------------*/

#define TXBUFINDEX     8
#define MAXLOGCHAN	  32	/* Max Number of Logical Channels on one SCC */


typedef struct bcsr 

{
	UWORD  bcsr0; /* Board Control and Status Register */
	UWORD  bcsr1;
	UWORD  bcsr2;
	UWORD  bcsr3;

} BCSR;


/*--------------------------------*/
/* Size of buffers in buffer pool */
/*--------------------------------*/

#define BUFFER_SIZE 256


/*---------------------------------------------------*/
/* Number of Receive and Transmit Buffer Descriptors */
/*---------------------------------------------------*/

#define NUM_RXBDS 8
#define NUM_TXBDS 8


/*-------------------------*/
/* Single buffer component */
/*-------------------------*/

typedef UBYTE LB[BUFFER_SIZE];

#define MAX_TXBD_INDEX	16
#define FIRST_TX_BUF 8

typedef struct BufferDescriptor 

{
   UHWORD bd_cstatus;     /* control and status */
   UHWORD bd_length;      /* transfer length */
   UBYTE  *bd_addr;       /* buffer address */

} BD;


/*--------------------------*/
/* Buffer Descriptor Format */
/*--------------------------*/

typedef struct BufferDescRings 

{
    BD RxBD[NUM_RXBDS];    /* Rx BD ring */
    BD TxBD[NUM_TXBDS];    /* Tx BD ring */

} BDRINGS;


#define BD_RX_ERROR 0xBF    /* Mask for set of Receive Buffer Errors,
                               including: DE, LG, NO, AB, CR, OV, CD */

/*-----------------------------------------------------------------*/
/* Number of Instructions in Vector Table for particular Interrupt */
/*-----------------------------------------------------------------*/

#define VECTOR_BLOCK_LEN 0x100


/*------------------------------------*/
/* SIU Vector Interrupt Code: Level 4 */
/*------------------------------------*/

#define IC_LEVEL_4  0x24


/*----------------------------------------------------------*/
/* SCC Interrupt Vector Code in CPM Vector Register (CIVR) */
/*----------------------------------------------------------*/

#define SCC1_VECTOR       0x1E
#define SCC2_VECTOR       0x1D
#define ETHEN 		  		  0x20000000	  /* ETHEN in bit 2 of BCSR1 */
#define READY_TO_RX_CMD   0              /* Ready to receive a command */



/*------------------------------*/
/* QMC Interrupt Circular Queue */
/*------------------------------*/

UHWORD IntCQ[MAXLOGCHAN];	/* Create the Interrupt Circular Queue */


/*----------------------------*/
/* Time Slot Assignment Table */
/*----------------------------*/

#define VALID_SLOT	0x8000
#define WRAP_SLOT  	0x4000