hdlcint.h

MPC860的SCC2配置HDLC示例代码

/*-----------------------------------------------------------------------------				
*
* File:  hdlcint.h
*
* Description:  
*
* 		Constants and Definitions for 8xx HDLC Driver. [Interrupt-driven 
*		version].
*
* History:
*
* 6/12/96    saw        Initial version.
* 2/20/97    sgj        Created HDLC version from IRDa version
* 8/26/97    sgj        Modified BD structure and cleaned up
* 11/20/97   jay        Modified BD structure and cleaned up
* 
*---------------------------------------------------------------------------*/

/*-------------------------------------------------------------------------*/
/*                     MPC8xx CONSTANTS AND DEFINITIONS                    */
/*-------------------------------------------------------------------------*/

#define INTERRUPT_LEVEL 4 	/* integer between 0 and 7 inclusive */

#define BASE_EVT 0x0  /* Base Address of Exception Vector Table */

#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  /* Base address of 
														      external interrupt 
														      code               */

#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)


/* ==================== APPLICATION CONSTANTS AND DEFINITIONS  =============== */

/*------------------------------------*/
/* Constants and Definitions for HDLC */
/*------------------------------------*/

#define HDLC_C_MASK    0xF0B8    /* CRC Constant */
#define HDLC_C_PRES    0xFFFF    /* CRC Preset */
#define HDLC_MAX_LEN   265       /* Maximum length of frame  */

#define STADDR    0x1999   /* HDLC Address for this receiver (station) */
#define TXBUFINDEX 8


typedef struct bcsr 

{
	UWORD  bcsr0; /* Board Control and Status Register */
	UWORD  bcsr1;
	UWORD  bcsr2;
	UWORD  bcsr3;

} BCSR;

/*--------------------------------*/
/* Size of buffers in buffer pool */
/*--------------------------------*/

#define BUFFER_SIZE 256

/*---------------------------------------------------*/
/* Number of Receive and Transmit Buffer Descriptors */
/*---------------------------------------------------*/

#define NUM_RXBDS 8
#define NUM_TXBDS 8

/*-------------------------*/
/* Single buffer component */
/*-------------------------*/

typedef UBYTE LB[BUFFER_SIZE];

#define MAX_TXBD_INDEX	16
#define FIRST_TX_BUF 8

typedef struct BufferDescriptor 

{
   UHWORD bd_cstatus;     /* control and status */
   UHWORD bd_length;      /* transfer length */
   UBYTE  *bd_addr;        /* buffer address */

} BD;

/*--------------------------*/
/* Buffer Descriptor Format */
/*--------------------------*/

typedef struct BufferDescRings 

{
    BD RxBD[NUM_RXBDS];    /* Rx BD ring */
    BD TxBD[NUM_TXBDS];    /* Tx BD ring */

} BDRINGS;

/*--------------------------------*/
/* Set of Supported Address modes */
/*--------------------------------*/

#define PROMISC 0x0000        /* Promiscuous - Mask all address bits */

#define SINGLE 0xFFFF          /* Single station - Compare all address bits */


#define BD_RX_ERROR 0xBF    /* Mask for set of Receive Buffer Errors,
                               including: DE, LG, NO, AB, CR, OV, CD */

/*-----------------------------------------------------------------*/
/* Number of Instructions in Vector Table for particular Interrupt */
/*-----------------------------------------------------------------*/

#define VECTOR_BLOCK_LEN 0x100

/*------------------------------------*/
/* SIU Vector Interrupt Code: Level 4 */
/*------------------------------------*/

#define IC_LEVEL_4  0x24

/*----------------------------------------------------------*/
/* SCC2 Interrupt Vector Code in CPM Vector Register (CIVR) */
/*----------------------------------------------------------*/

#define SCC2_VECTOR 0x1D

#define	ETHEN	0x20000000	   /* ETHEN in bit 2 of BCSR1 */

#define  READY_TO_RX_CMD   0  /* Ready to receive a command */