📄 hdlcint.c
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/*----------------*/
/* Load 254 0xFFs */
/*----------------*/
/*--------------------------------*/
/* Load the destination address */
/*--------------------------------*/
BufferPool[FIRST_TX_BUF+3][0] = (STADDR%256); /* Load the low byte first */
BufferPool[FIRST_TX_BUF+3][1] = (STADDR/256); /* Load the high byte */
for (index = 2; index < BUFFER_SIZE; index++)
{
BufferPool[FIRST_TX_BUF+3][index] = 0xFF;
}
/*------------------------------*/
/* Load increasing walking ones */
/*------------------------------*/
/*--------------------------------*/
/* Load the destination address */
/*--------------------------------*/
BufferPool[FIRST_TX_BUF+4][0] = (STADDR%256); /* Load the low byte first */
BufferPool[FIRST_TX_BUF+4][1] = (STADDR/256); /* Load the high byte */
for (index = 2,pattern = 1; index < BUFFER_SIZE; index++,pattern<<=1)
{
if (pattern == 0x0100)
pattern = 0x01;
BufferPool[FIRST_TX_BUF+4][index] = pattern;
}
/*------------------------------*/
/* Load decreasing walking ones */
/*------------------------------*/
/*--------------------------------*/
/* Load the destination address */
/*--------------------------------*/
BufferPool[FIRST_TX_BUF+5][0] = (STADDR%256); /* Load the low byte first */
BufferPool[FIRST_TX_BUF+5][1] = (STADDR/256); /* Load the high byte */
for (index = 2,pattern = 0x80; index < BUFFER_SIZE; index++,pattern>>=1)
{
if (pattern == 0x00)
pattern = 0x80;
BufferPool[FIRST_TX_BUF+5][index] = pattern;
}
/*---------------------------------*/
/* Load "Increment from 0" pattern */
/*---------------------------------*/
/*--------------------------------*/
/* Load the destination address */
/*--------------------------------*/
BufferPool[FIRST_TX_BUF+6][0] = (STADDR%256); /* Load the low byte first */
BufferPool[FIRST_TX_BUF+6][1] = (STADDR/256); /* Load the high byte */
for (index = 2; index < BUFFER_SIZE; index++)
{
BufferPool[FIRST_TX_BUF+6][index] = index-2;
}
/*-----------------------------------*/
/* Load "Decrement from 255" pattern */
/*-----------------------------------*/
/*--------------------------------*/
/* Load the destination address */
/*--------------------------------*/
BufferPool[FIRST_TX_BUF+7][0] = (STADDR%256); /* Load the low byte first */
BufferPool[FIRST_TX_BUF+7][1] = (STADDR/256); /* Load the high byte */
for (index = 2; index < BUFFER_SIZE; index++)
{
BufferPool[FIRST_TX_BUF+7][index] = (257-index);;
}
} /* end of LoadTxBuffers */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: SCC2HInit
*
* DESCRIPTION:
*
* SCC2 HDLC Initialization Routine. Initialize for External Interrupt Rx/Tx
* HDLC. Initialize 8xx for External Interrupt SCC2 HDLC.
*
* EXTERNAL EFFECT:
*
* Parameter Ram and various registers on the 860 including interrupt related
* registers and port registers. This function, when complete will initiate or
* start the transfer of 8 HDLC frames of data.
*
* PARAMETERS: None
*
* RETURNS: None
*
*----------------------------------------------------------------------------*/
void SCC2HInit()
{
/*---------------------------------------------*/
/* Configure Port A pins to enable RXD2, TXD2. */
/*---------------------------------------------*/
IMMR->pio_papar |= 0x000C;
/*-----------------------------------------------------------------------*/
/* These two bits must be zero when these two port A pins are configured */
/* as on-chip dedicated peripheral. */
/*-----------------------------------------------------------------------*/
IMMR->pio_padir &= 0xFFF3;
/*-------------------------------------------------------------------*/
/* Initialize baud rate generator. My Motorola ADS target is */
/* configured to have a 24Mhz clock out of the system PLL. The 24Mhz */
/* internal clock will be divided down by 12 to give a baud clock of */
/* 2Mhz. CD bits will be programmed to 0xB. They are not programmed */
/* to 0xC because total divide ratio is CD value+1 {can never divide */
/* by 0}. */
/*-------------------------------------------------------------------*/
IMMR->brgc4 = (0x00010016); /* Enable BRG with division factor 12 */
/*---------------------------------------------------------*/ /* Initialize the SI Clock Route Register (SICR) for SCC2. */
/* */
/* - Connect SCC2 to NMSI, */
/* - Transmit Clock = BRG4, Receive Clock = BRG4 */
/*---------------------------------------------------------*/ IMMR->si_sicr &= (0xFFFF00FF); /* Clear previous scc2 setting */
IMMR->si_sicr |= (0x00001B00); /* Setup scc2 */
/*************************************************************/
/* HDLC Specific Parameter RAM Initialization. */
/*************************************************************/
/*---------------------------------------------*/
/* Initialize CRC Mask to use 16 bit CRC-CCITT */
/*---------------------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.c_mask = HDLC_C_MASK;
IMMR->PRAM[PAGE2].pg.scc.h.c_pres = HDLC_C_PRES; /* CRC Preset */
IMMR->PRAM[PAGE2].pg.scc.h.disfc = 0; /* Clear Discard Frame Counter */
IMMR->PRAM[PAGE2].pg.scc.h.crcec = 0; /* Clear CRC Error Counter */
IMMR->PRAM[PAGE2].pg.scc.h.abtsc = 0; /* Clear Abort Sequence Counter */
IMMR->PRAM[PAGE2].pg.scc.h.nmarc = 0; /* Clear Nonmatching RX Address Counter */
IMMR->PRAM[PAGE2].pg.scc.h.retrc = 0; /* Clear Frame Re-transmission Counter */
IMMR->PRAM[PAGE2].pg.scc.h.rfthr = 1; /* Rx Frames Threshold */
IMMR->PRAM[PAGE2].pg.scc.h.mflr = HDLC_MAX_LEN; /* Maximum Frame Length */
/*-------------------*/
/* Mask all the bits */
/*-------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.hmask = ALL_ONES;
/*-----------------------------------------------------------------------*/
/* Establish addresses that the HDLC controller will be watching out for */
/*-----------------------------------------------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.haddr1 = 0xFFFF; /* Broadcast Address */
IMMR->PRAM[PAGE2].pg.scc.h.haddr2 = STADDR; /* Rx Station Address */
IMMR->PRAM[PAGE2].pg.scc.h.haddr3 = 0xFFFF; /* Dummy */
IMMR->PRAM[PAGE2].pg.scc.h.haddr4 = 0xFFFF; /* Dummy */
/*--------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/*--------------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.rfcr = 0x18; /* Normal Operation and Motorola
byte ordering */
IMMR->PRAM[PAGE2].pg.scc.h.tfcr = 0x18; /* Motorola byte ordering, Normal
access */
/*------------------------------------------------*/
/* Set RBASE,TBASE -- Rx,Tx Buffer Base Addresses */
/*------------------------------------------------*/
/*---------------------------------*/
/* Set RXBD tbl start at Dual Port */
/*---------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.rbase = (UHWORD)&RxTxBD->RxBD[0];
/*---------------------------------*/
/* Set TXBD tbl start at Dual Port */
/*---------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.tbase = (UHWORD)&RxTxBD->TxBD[0];
/*-----------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/*-----------------------------------------*/
IMMR->PRAM[PAGE2].pg.scc.h.mrblr = BUFFER_SIZE;
/*-------------------------------------------------*/
/* Initialize GSMR High 32-Bits Settings: Default */
/*-------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_gsmr_h = 0;
/*-----------------------------------------------------------------*/
/* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive */
/* Settings: */
/* (DIAG = Local Loopback) -- For Local Loopback Mode ONLY */
/* MODE = HDLC */
/*-----------------------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_gsmr_l = 0;
IMMR->scc_regs[SCC2_REG].scc_gsmr_l |= GSMR_L1_INT_LB; /* int loopback */
/*-----------------------------------------*/
/* Clear SCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_scce = ALL_ONES;
/*----------------------------------------------------------------*/
/* Write CIMR to Enable Interrupts to the CP Interrupt Controller */
/* Enable SCC2 Interrupts */
/*----------------------------------------------------------------*/
IMMR->cpmi_cimr = CIMR_SCC2;
/*-------------------------------------------------------------*/
/* Clear Pending Interrupts in CIPR -- Clear bits by writing 1 */
/*-------------------------------------------------------------*/
IMMR->cpmi_cipr = ALL_ONES;
/*-----------------------------------------------*/
/* Set Appropriate Interrupt Level Bit in SIMASK */
/*-----------------------------------------------*/
switch(INTERRUPT_LEVEL)
{
case 0:
IMMR->siu_simask = SIMASK_LVM0;
break;
case 1:
IMMR->siu_simask = SIMASK_LVM1;
break;
case 2:
IMMR->siu_simask = SIMASK_LVM2;
break;
case 3:
IMMR->siu_simask = SIMASK_LVM3;
break;
case 4:
IMMR->siu_simask = SIMASK_LVM4;
break;
case 5:
IMMR->siu_simask = SIMASK_LVM5;
break;
case 6:
IMMR->siu_simask = SIMASK_LVM6;
break;
case 7:
IMMR->siu_simask = SIMASK_LVM7;
break;
default:
break; /* Bad value */
} /* end switch */
/*-----------------------------------------------------------------*/
/* Write SCCM to Enable Interrupts. Interrupt on Following Events: */
/* Rx Frame -- Complete Frame Received */
/*-----------------------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_sccm = HDLC_SCCM_RXF;
/*----------------------------------------------------------------*/
/* Write CICR to Configure SCC2 Interrupt Priority Settings: */
/* */
/* SCC Priorities */
/* SCC2 - Highest Priority */
/* IRL0-IRL2 (Interrupt Request Level) = Constant set by user */
/* HP0-HP4 (Highest Priority) = Original Priority */
/* IEN = Enable CPM Interrupts */
/*----------------------------------------------------------------*/
IMMR->cpmi_cicr = 0xE11F80 | (INTERRUPT_LEVEL << 13);
/*---------------------------------------------------------------------*/
/* Initialize the SCC Data Syncronization Reg (DSR). Program 7E flags */
/* as syncronization flags. */
/*---------------------------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_dsr = DSR_HDLC;
/*------------------------------------------------*/
/* Program PSMR. 16-bit CCITT CRC. 2 flag minimum */
/*------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_psmr = HDLC_PSMR_NOF_2;
/*-----------------------------------------*/ /* Enable External Interrupts at CPU level */
/*-----------------------------------------*/
#ifdef MetaWare
_ASM(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#else
#ifdef Diab
asm(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#endif
#endif
/*----------------------------------------------------------------------*/
/* Issue Init RX & TX Parameters Command for SCC2. This command to the */
/* CP lets it know to reinitialize SCC2 with the new parameter RAM */
/* values. When the ENT/ENR bits are set below Hunt Mode will begin */
/* automatically. */
/*----------------------------------------------------------------------*/
while ((IMMR->cp_cr & CPCR_FLG) != READY_TO_RX_CMD);
IMMR->cp_cr = CPCR_INIT_TX_RX_PARAMS |
CPCR_SCC2_CH |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMMR->cp_cr & CPCR_FLG) != READY_TO_RX_CMD);
/*-------------------------------------------------------------*/
/* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */
/*-------------------------------------------------------------*/
IMMR->scc_regs[SCC2_REG].scc_gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR;
} /* end SCC2HInit() */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptInit
*
* DESCRIPTION:
*
* Copy Interrupt Handler code from its current address to the specified
* PowerPC Interrupt Vector.
*
* EXTERNAL EFFECTS:
*
* PARAMETERS:
*
* interrupt_vector -- address to which interrupt code should be copied
* interrupt_code -- current address of interrupt code
*
* RETURNS: NONE
*
*-----------------------------------------------------------------------------*/
void InterruptInit(UWORD *interrupt_vector,
UWORD interrupt_code[])
{
UHWORD index;
UWORD *instruction;
UWORD *next_vector;
next_vector = (interrupt_vector + VECTOR_BLOCK_LEN); /* next vector entry */
for(instruction = interrupt_vector, index = 0; instruction < next_vector;
instruction++, index++)
*instruction = interrupt_code[index];
} /* end InterruptInit */
/*-----------------------------------------------------------------------------
*
* FUNCTION NAME: BDRxError
*
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