📄 mpc860.h
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UHWORD tlbd_ptr; /* tx last bd pointer */
UWORD tbuf1_data0; /* save area 0 - next frame */
UWORD tbuf1_data1; /* save area 1 - next frame */
UWORD tbuf1_rba0;
UWORD tbuf1_crc;
UHWORD tbuf1_bcnt;
UHWORD tx_len; /* tx frame length counter */
UHWORD iaddr1; /* individual address filter 1*/
UHWORD iaddr2; /* individual address filter 2*/
UHWORD iaddr3; /* individual address filter 3*/
UHWORD iaddr4; /* individual address filter 4*/
UHWORD boff_cnt; /* back-off counter */
UHWORD taddr_h; /* temp address (MSB) */
UHWORD taddr_m; /* temp address */
UHWORD taddr_l; /* temp address (LSB) */
};
/*--------------------------------------------------------------------------*/
/* SMC UART parameter RAM */
/*--------------------------------------------------------------------------*/
struct smc_uart_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD max_idl; /* Maximum IDLE Characters */
UHWORD idlc; /* Temporary IDLE Counter */
UHWORD brkln; /* Last Rx Break Length */
UHWORD brkec; /* Rx Break Condition Counter */
UHWORD brkcr; /* Break Count Register (Tx) */
UHWORD r_mask; /* Temporary bit mask */
};
/*--------------------------------------------------------------------------*/
/* SMC Transparent mode parameter RAM */
/*--------------------------------------------------------------------------*/
struct smc_trnsp_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD reserved[5]; /* Reserved */
};
/*--------------------------------------------------------------------------*/
/* SPI parameter RAM */
/*--------------------------------------------------------------------------*/
#define SPI_R 0x8000 /* Ready bit in BD */
struct spi_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
};
/*--------------------------------------------------------------------------*/
/* I2C parameter RAM */
/*--------------------------------------------------------------------------*/
struct i2c_pram
{
/*--------------------*/
/* I2C parameter RAM */
/*--------------------*/
UHWORD rbase; /* RX BD base address */
UHWORD tbase; /* TX BD base address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
};
/*--------------------------------------------------------------------------*/
/* PIP Centronics parameter RAM */
/*--------------------------------------------------------------------------*/
struct centronics_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE fcr; /* function code */
UBYTE smask; /* Status Mask */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD max_sl; /* Maximum Silence period */
UHWORD sl_cnt; /* Silence Counter */
UHWORD char1; /* CONTROL char 1 */
UHWORD char2; /* CONTROL char 2 */
UHWORD char3; /* CONTROL char 3 */
UHWORD char4; /* CONTROL char 4 */
UHWORD char5; /* CONTROL char 5 */
UHWORD char6; /* CONTROL char 6 */
UHWORD char7; /* CONTROL char 7 */
UHWORD char8; /* CONTROL char 8 */
UHWORD rccm; /* Rx Control Char Mask */
UHWORD rccr; /* Rx Char Control Register */
};
/*--------------------------------------------------------------------------*/
/* IDMA parameter RAM */
/*--------------------------------------------------------------------------*/
struct idma_pram
{
UHWORD ibase; /* IDMA BD Base Address */
UHWORD ibptr; /* IDMA buffer descriptor pointer */
UWORD istate; /* IDMA internal state */
UWORD itemp; /* IDMA temp */
};
/*--------------------------------------------------------------------------*/
/* RISC timer parameter RAM */
/*--------------------------------------------------------------------------*/
struct timer_pram
{
/*----------------------------*/
/* RISC timers parameter RAM */
/*----------------------------*/
UHWORD tm_base; /* RISC timer table base adr */
UHWORD tm_ptr; /* RISC timer table pointer */
UHWORD r_tmr; /* RISC timer mode register */
UHWORD r_tmv; /* RISC timer valid register */
UWORD tm_cmd; /* RISC timer cmd register */
UWORD tm_cnt; /* RISC timer internal cnt */
};
/*--------------------------------------------------------------------------*/
/* ROM Microcode parameter RAM */
/*--------------------------------------------------------------------------*/
struct ucode_pram
{
/*---------------------------*/
/* RISC ucode parameter RAM */
/*---------------------------*/
UHWORD rev_num; /* Ucode Revision Number */
UHWORD d_ptr; /* MISC Dump area pointer */
UWORD temp1; /* MISC Temp1 */
UWORD temp2; /* MISC Temp2 */
};
/***************************************************************************/
/* */
/* Definitions of Embedded PowerPC (EPPC) internal memory structures, */
/* including registers and dual-port RAM */
/* */
/***************************************************************************/
typedef struct eppc
{
/*-----------------------------------*/
/* BASE + 0x0000: INTERNAL REGISTERS */
/*-----------------------------------*/
/*-----*/
/* SIU */
/*-----*/
VUWORD siu_mcr; /* module configuration reg */
VUWORD siu_sypcr; /* System protection cnt */
UBYTE RESERVED58[0x6];
VUHWORD siu_swsr; /* sw service */
VUWORD siu_sipend; /* Interrupt pend reg */
VUWORD siu_simask; /* Interrupt mask reg */
VUWORD siu_siel; /* Interrupt edge level mask reg */
VUWORD siu_sivec; /* Interrupt vector */
VUWORD siu_tesr; /* Transfer error status */
VUBYTE RESERVED1[0xc]; /* Reserved area */
VUWORD dma_sdcr; /* SDMA configuration reg */
UBYTE RESERVED55[0x4c];
/*--------*/
/* PCMCIA */
/*--------*/
VUWORD pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
VUWORD pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
VUWORD pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
VUWORD pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
VUWORD pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
VUWORD pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
VUWORD pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
VUWORD pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
VUWORD pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
VUWORD pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
VUWORD pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
VUWORD pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
VUWORD pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
VUWORD pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
VUWORD pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
VUWORD pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
VUBYTE RESERVED2[0x20]; /* Reserved area */
VUWORD pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
VUWORD pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
VUWORD pcmcia_pscr; /* PCMCIA Status Reg */
VUBYTE RESERVED2a[0x4]; /* Reserved area */
VUWORD pcmcia_pipr; /* PCMCIA Pins Value Reg */
VUBYTE RESERVED2b[0x4]; /* Reserved area */
VUWORD pcmcia_per; /* PCMCIA Enable Reg */
VUBYTE RESERVED2c[0x4]; /* Reserved area */
/*------*/
/* MEMC */
/*------*/
VUWORD memc_br0; /* base register 0 */
VUWORD memc_or0; /* option register 0 */
VUWORD memc_br1; /* base register 1 */
VUWORD memc_or1; /* option register 1 */
VUWORD memc_br2; /* base register 2 */
VUWORD memc_or2; /* option register 2 */
VUWORD memc_br3; /* base register 3 */
VUWORD memc_or3; /* option register 3 */
VUWORD memc_br4; /* base register 3 */
VUWORD memc_or4; /* option register 3 */
VUWORD memc_br5; /* base register 3 */
VUWORD memc_or5; /* option register 3 */
VUWORD memc_br6; /* base register 3 */
VUWORD memc_or6; /* option register 3 */
VUWORD memc_br7; /* base register 3 */
VUWORD memc_or7; /* option register 3 */
VUBYTE RESERVED3[0x24]; /* Reserved area */
VUWORD memc_mar; /* Memory address */
VUWORD memc_mcr; /* Memory command */
VUBYTE RESERVED4[0x4]; /* Reserved area */
VUWORD memc_mamr; /* Machine A mode */
VUWORD memc_mbmr; /* Machine B mode */
VUHWORD memc_mstat; /* Memory status */
VUHWORD memc_mptpr; /* Memory preidic timer prescalar */
VUWORD memc_mdr; /* Memory data */
VUBYTE RESERVED5[0x80]; /* Reserved area */
/*---------------------------*/
/* SYSTEM INTEGRATION TIMERS */
/*---------------------------*/
VUHWORD simt_tbscr; /* Time base stat&ctr */
VUBYTE RESERVED100[0x2]; /* Reserved area */
VUWORD simt_tbreff0; /* Time base reference 0 */
VUWORD simt_tbreff1; /* Time base reference 1 */
VUBYTE RESERVED6[0x14]; /* Reserved area */
VUHWORD simt_rtcsc; /* Realtime clk stat&cntr 1 */
VUBYTE RESERVED110[0x2]; /* Reserved area */
VUWORD simt_rtc; /* Realtime clock */
VUWORD simt_rtsec; /* Realtime alarm seconds */
VUWORD simt_rtcal; /* Realtime alarm */
VUBYTE RESERVED56[0x10]; /* Reserved area */
VUWORD simt_piscr; /* PIT stat&ctrl */
VUWORD simt_pitc; /* PIT counter */
VUWORD simt_pitr; /* PIT */
VUBYTE RESERVED7[0x34]; /* Reserved area */
/*---------------*/
/* CLOCKS, RESET */
/*---------------*/
VUWORD clkr_sccr; /* System clk cntrl */
VUWORD clkr_plprcr; /* PLL reset&ctrl */
VUWORD clkr_rsr; /* reset status */
UBYTE RESERVED8a[0x74]; /* Reserved area */
/*--------------------------------*/
/* System Integration Timers Keys */
/*--------------------------------*/
VUWORD simt_tbscrk; /* Timebase Status&Ctrl Key */
VUWORD simt_tbreff0k; /* Timebase Reference 0 Key */
VUWORD simt_tbreff1k; /* Timebase Reference 1 Key */
VUWORD simt_tbk; /* Timebase and Decrementer Key */
UBYTE RESERVED66b[0x10]; /* Reserved area */
VUWORD simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
VUWORD simt_rtck; /* Real-Time Clock Key */
VUWORD simt_rtseck; /* Real-Time Alarm Seconds Key */
VUWORD simt_rtcalk; /* Real-Time Alarm Key */
UBYTE RESERVED66c[0x10]; /* Reserved area */
VUWORD simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
VUWORD simt_pitck; /* Periodic Interrupt Count Key */
UBYTE RESERVED66d[0x38]; /* Reserved area */
/*----------------------*/
/* Clock and Reset Keys */
/*----------------------*/
VUWORD clkr_sccrk; /* System Clock Control Key */
VUWORD clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
VUWORD clkr_rsrk; /* Reset Status Key */
UBYTE RESERVED66e[0x4d4]; /* Reserved area */
/*-----*/
/* I2C */
/*-----*/
VUBYTE i2c_i2mod; /* i2c mode */
UBYTE RESERVED59[3];
VUBYTE i2c_i2add; /* i2c address */
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