📄 patch-2.4.19-rmk-arm-rthal5
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next_match = (OSMR0 += LATCH);+#ifdef CONFIG_RTHAL+ rthal.timer_match = next_match;+#endif local_irq_restore(flags); do_set_rtc(); } while ((signed long)(next_match - OSCR) <= 0);diff -urNp --exclude=CVS linux-2.4.19-rmk7-tux1/include/asm-arm/atomic.h linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/atomic.h--- linux-2.4.19-rmk7-tux1/include/asm-arm/atomic.h Tue Aug 12 22:31:30 2003+++ linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/atomic.h Fri Dec 26 00:30:53 2003@@ -27,7 +27,18 @@ typedef struct { volatile int counter; } #define ATOMIC_INIT(i) { (i) } #ifdef __KERNEL__++#ifdef CONFIG_RTHAL+/* RTAI Modification, azu */+#include <asm/proc/hard_system.h>+#define _atomic_irq_save(x) hard_local_irq_save(x)+#define _atomic_irq_restore(x) hard_local_irq_restore(x)+#else+/* Normal mode */ #include <asm/proc/system.h>+#define _atomic_irq_save(x) local_irq_save(x)+#define _atomic_irq_restore(x) local_irq_restore(x)+#endif #define atomic_read(v) ((v)->counter) #define atomic_set(v,i) (((v)->counter) = (i))@@ -36,36 +47,36 @@ static inline void atomic_add(int i, vol { unsigned long flags; - local_irq_save(flags);+ _atomic_irq_save(flags); v->counter += i;- local_irq_restore(flags);+ _atomic_irq_restore(flags); } static inline void atomic_sub(int i, volatile atomic_t *v) { unsigned long flags; - local_irq_save(flags);+ _atomic_irq_save(flags); v->counter -= i;- local_irq_restore(flags);+ _atomic_irq_restore(flags); } static inline void atomic_inc(volatile atomic_t *v) { unsigned long flags; - local_irq_save(flags);+ _atomic_irq_save(flags); v->counter += 1;- local_irq_restore(flags);+ _atomic_irq_restore(flags); } static inline void atomic_dec(volatile atomic_t *v) { unsigned long flags; - local_irq_save(flags);+ _atomic_irq_save(flags); v->counter -= 1;- local_irq_restore(flags);+ _atomic_irq_restore(flags); } static inline int atomic_dec_and_test(volatile atomic_t *v)@@ -73,10 +84,10 @@ static inline int atomic_dec_and_test(vo unsigned long flags; int val; - local_irq_save(flags);+ _atomic_irq_save(flags); val = v->counter; v->counter = val -= 1;- local_irq_restore(flags);+ _atomic_irq_restore(flags); return val == 0; }@@ -86,10 +97,10 @@ static inline int atomic_add_negative(in unsigned long flags; int val; - local_irq_save(flags);+ _atomic_irq_save(flags); val = v->counter; v->counter = val += i;- local_irq_restore(flags);+ _atomic_irq_restore(flags); return val < 0; }@@ -98,9 +109,9 @@ static inline void atomic_clear_mask(uns { unsigned long flags; - local_irq_save(flags);+ _atomic_irq_save(flags); *addr &= ~mask;- local_irq_restore(flags);+ _atomic_irq_restore(flags); } /* Atomic operations are already serializing on ARM */diff -urNp --exclude=CVS linux-2.4.19-rmk7-tux1/include/asm-arm/mach/irq.h linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/mach/irq.h--- linux-2.4.19-rmk7-tux1/include/asm-arm/mach/irq.h Thu Jun 19 10:54:34 2003+++ linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/mach/irq.h Tue Dec 23 23:05:13 2003@@ -18,7 +18,8 @@ struct irqdesc { unsigned int probe_ok : 1; /* IRQ can be used for probe */ unsigned int valid : 1; /* IRQ claimable */ unsigned int noautoenable : 1; /* don't automatically enable IRQ */- unsigned int unused :25;+ unsigned int masked : 1; /* IRQ is masked */+ unsigned int unused :24; unsigned int disable_depth; struct list_head pend;diff -urNp --exclude=CVS linux-2.4.19-rmk7-tux1/include/asm-arm/pgalloc.h linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/pgalloc.h--- linux-2.4.19-rmk7-tux1/include/asm-arm/pgalloc.h Wed Aug 13 00:03:42 2003+++ linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/pgalloc.h Fri Dec 26 00:30:53 2003@@ -138,4 +138,33 @@ static inline pgd_t *pgd_alloc(struct mm extern int do_check_pgt_cache(int, int); +#ifdef CONFIG_RTHAL+extern inline void set_pgdir(unsigned long address, pgd_t entry)+{+ struct task_struct * p;+ pgd_t *pgd;+#ifdef CONFIG_SMP+ int i;+#endif++ read_lock(&tasklist_lock);+ for_each_task(p) {+ if (!p->mm)+ continue;+ *pgd_offset(p->mm,address) = entry;+ }+ read_unlock(&tasklist_lock);+#ifndef CONFIG_SMP+ for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)__pgd_next(pgd))+ pgd[pgd_index(address)] = entry;+#else+ /* To pgd_alloc/pgd_free, one holds master kernel lock and so does our callee, so we can+ modify pgd caches of other CPUs as well. -jj */+ for (i = 0; i < NR_CPUS; i++)+ for (pgd = (pgd_t *)cpu_data[i].pgd_quick; pgd; pgd = (pgd_t *)__pgd_next(pgd))+ pgd[pgd_index(address)] = entry;+#endif+}+#endif /* CONFIG_RTHAL */+ #endifdiff -urNp --exclude=CVS linux-2.4.19-rmk7-tux1/include/asm-arm/proc-armv/hard_system.h linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/proc-armv/hard_system.h--- linux-2.4.19-rmk7-tux1/include/asm-arm/proc-armv/hard_system.h Thu Jan 1 01:00:00 1970+++ linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/proc-armv/hard_system.h Tue Oct 7 12:16:07 2003@@ -0,0 +1,124 @@+/*+ * linux/include/asm-arm/proc-armv/hard_system.h+ *+ * Copyright (C) 1996 Russell King+ *+ * This program is free software; you can redistribute it and/or modify+ * it under the terms of the GNU General Public License version 2 as+ * published by the Free Software Foundation.+ */++/*+ * RTAI+ * The hard manipulation for enabling/disabling interrupts and related stuff.+ */++#ifndef __ASM_PROC_HARD_SYSTEM_H+#define __ASM_PROC_HARD_SYSTEM_H++#include <linux/config.h>++/*+ * Save the current interrupt enable state & disable IRQs+ */+#define hard_local_irq_save(x) \+ ({ \+ unsigned long temp; \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ local_irq_save\n" \+" orr %1, %0, #128\n" \+" msr cpsr_c, %1" \+ : "=r" (x), "=r" (temp) \+ : \+ : "memory"); \+ })+ +/*+ * Enable IRQs+ */+#define hard_local_irq_enable() \+ ({ \+ unsigned long temp; \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ local_irq_enable\n" \+" bic %0, %0, #128\n" \+" msr cpsr_c, %0" \+ : "=r" (temp) \+ : \+ : "memory"); \+ })++/*+ * Disable IRQs+ */+#define hard_local_irq_disable() \+ ({ \+ unsigned long temp; \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ local_irq_disable\n" \+" orr %0, %0, #128\n" \+" msr cpsr_c, %0" \+ : "=r" (temp) \+ : \+ : "memory"); \+ })++/*+ * Enable FIQs+ */+#define hard_stf() \+ ({ \+ unsigned long temp; \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ stf\n" \+" bic %0, %0, #64\n" \+" msr cpsr_c, %0" \+ : "=r" (temp) \+ : \+ : "memory"); \+ })++/*+ * Disable FIQs+ */+#define hard_clf() \+ ({ \+ unsigned long temp; \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ clf\n" \+" orr %0, %0, #64\n" \+" msr cpsr_c, %0" \+ : "=r" (temp) \+ : \+ : "memory"); \+ })++/*+ * Save the current interrupt enable state.+ */+#define hard_local_save_flags(x) \+ ({ \+ __asm__ __volatile__( \+ "mrs %0, cpsr @ local_save_flags\n" \+ : "=r" (x) \+ : \+ : "memory"); \+ })++/*+ * restore saved IRQ & FIQ state+ */+#define hard_local_irq_restore(x) \+ __asm__ __volatile__( \+ "msr cpsr_c, %0 @ local_irq_restore\n" \+ : \+ : "r" (x) \+ : "memory")++#define hard_cli() hard_local_irq_disable()+#define hard_sti() hard_local_irq_enable()+#define hard_save_flags_cli(x) hard_local_irq_save(x)+#define hard_restore_flags(x) hard_local_irq_restore(x)+#define hard_save_flags(x) hard_local_save_flags(x)++#endifdiff -urNp --exclude=CVS linux-2.4.19-rmk7-tux1/include/asm-arm/proc-armv/system.h linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/proc-armv/system.h--- linux-2.4.19-rmk7-tux1/include/asm-arm/proc-armv/system.h Tue Aug 12 22:31:30 2003+++ linux-2.4.19-rmk7-tux1-rthal/include/asm-arm/proc-armv/system.h Fri Dec 26 00:30:51 2003@@ -42,6 +42,37 @@ extern unsigned long cr_alignment; /* de #define vectors_base() (0) #endif +#ifdef CONFIG_RTHAL+#include <asm/proc/ptrace.h>++/*+ * RTAI+ * Definition of rthal.+ * Do not change this structure unless you know what you are doing!+ * Filled with values in arch/arm/kernel/irq.c+ */++struct rt_hal {+ void (*do_IRQ)(int, struct pt_regs*); /* must be first - arch/arm/kernel/entry-armv.S */+ long long (*do_SRQ)(int, unsigned long); /* must be second - arch/arm/kernel/entry-common.S */+ int (*do_TRAP)(int, struct pt_regs*); /* must be third - arch/arm/kernel/entry-armv.S */+ void (*disint)(void);+ void (*enint)(void);+ unsigned int (*getflags)(void);+ void (*setflags)(unsigned int);+ unsigned int (*getflags_and_cli)(void);+ void (*fdisint)(void);+ void (*fenint)(void);+ volatile u32 timer_match; /* Soft next Linux timer-interrupt */+ void (*copy_back)(unsigned long, int);+ void (*c_do_IRQ)(int, struct pt_regs*);+} __attribute__ ((__aligned__ (32)));++volatile extern struct rt_hal rthal;++#endif++#ifndef CONFIG_RTHAL /* * Save the current interrupt enable state & disable IRQs */@@ -139,6 +170,18 @@ extern unsigned long cr_alignment; /* de : "r" (x) \ : "memory") +#else+#define local_irq_save(x) do { x = rthal.getflags_and_cli(); } while (0)+#define local_irq_enable() do { rthal.enint(); } while (0)+#define local_irq_disable() do { rthal.disint(); } while (0)+#define __stf() do { rthal.fenint(); } while (0)+#define __clf() do { rthal.fdisint(); } while (0)+#define local_save_flags(x) do { x = rthal.getflags(); } while (0)+#define local_irq_restore(x) do { rthal.setflags(x); } while (0)++#include <asm/proc/hard_system.h>+#endif + #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) /* * On the StrongARM, "swp" is terminally broken since it bypasses the@@ -165,6 +208,7 @@ static inline unsigned long __xchg(unsig switch (size) { #ifdef swp_is_buggy+#ifndef CONFIG_RTHAL /* original stuff */ case 1: local_irq_save(flags); ret = *(volatile unsigned char *)ptr;@@ -178,6 +222,21 @@ static inline unsigned long __xchg(unsig *(volatile unsigned long *)ptr = x; local_irq_restore(flags); break;+#else /* CONFIG_RTHAL keep it atomic */+ case 1:+ hard_local_irq_save(flags);+ ret = *(volatile unsigned char *)ptr;+ *(volatile unsigned char *)ptr = x;+ hard_local_irq_restore(flags);+ break;++ case 4:+ hard_local_irq_save(flags);+ ret = *(volatile unsigned long *)ptr;+ *(volatile unsigned long *)ptr = x;+ hard_local_irq_restore(flags);+ break;+#endif /* CONFIG_RTHAL */ #else case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" : "=&r" (ret)⌨️ 快捷键说明
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