ddr_compile_all.v

来自「sdram的verilog的源码实现」· Verilog 代码 · 共 11 行

`include "ddr_command.v"
`include "ddr_sdram.v"
`include "ddr_control_interface.v"
`include "ddr_sdram_tb.v"
`include "mt46v4m16.v"
`include "ddr_data_path.v"
`include "pll1.v"
`include "altclklock.v"