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📁 Verilog DHL教程
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch09.css"><TITLE> Section 9</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="none">Chapter&nbsp;&nbsp;start</A>&nbsp;&nbsp;&nbsp;<A HREF="ch09.1.htm">Next&nbsp;&nbsp;page</A></P></DIV><DIV><H1 CLASS="Chapter"><A NAME="pgfId=382"> </A>Section 9<A NAME="73702"> </A></H1><H1 CLASS="ChapterTitle"><A NAME="pgfId=512"> </A><A NAME="81600"> </A><A NAME="marker=10"> </A><A NAME="marker=11"> </A>Behavioral modeling </H1><P CLASS="Body"><A NAME="pgfId=513"> </A>The language constructs introduced so far allow hardware to be described at a relatively detailed level. Modeling a circuit with logic gates and continuous assignments reflects quite closely the logic structure of the circuit being modeled; however, these constructs do not provide the power of abstraction necessary for describing complex high level aspects of a system. The procedural constructs described in this section are well suited to tackling problems such as describing a microprocessor or implementing complex timing checks.</P><P CLASS="Body"><A NAME="pgfId=514"> </A>This section starts with a brief overview of a behavioral model to provide a context for many types of behavioral statements in Verilog HDL. </P><H2 CLASS="SectionTOC"><A HREF="ch09.1.htm#pgfId=516" CLASS="Hypertext">9.1	Behavioral model overview </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.2.htm#pgfId=431" CLASS="Hypertext">9.2	Procedural assignments </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.3.htm#pgfId=500" CLASS="Hypertext">9.3	Procedural continuous assignments </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.4.htm#pgfId=591" CLASS="Hypertext">9.4	Conditional statement </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.5.htm#pgfId=541" CLASS="Hypertext">9.5	Case statement </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.6.htm#pgfId=660" CLASS="Hypertext">9.6	Looping statements</A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.7.htm#pgfId=685" CLASS="Hypertext">9.7	Procedural timing controls </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.8.htm#pgfId=747" CLASS="Hypertext">9.8	Block statements </A></H2><H2 CLASS="SectionTOC"><A HREF="ch09.9.htm#pgfId=790" CLASS="Hypertext">9.9	Structured procedures </A></H2></DIV><HR><P><A HREF="none">Chapter&nbsp;&nbsp;start</A>&nbsp;&nbsp;&nbsp;<A HREF="ch09.1.htm">Next&nbsp;&nbsp;page</A></P></BODY></HTML>

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