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<HTML><HEAD> <META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac"> <LINK REL="STYLESHEET" HREF="ch04.css"> <TITLE> Section 4</TITLE></HEAD><BODY BGCOLOR="#ffffff"><P><A NAME="pgfId=462"></A><HR ALIGN="LEFT"></P><P><A HREF="../../../Verilog.htm">Back to Verilog LRM index</A> <A HREF="ch04.htm">Next Section (disabled)</A> <A HREF="../03/ch03.htm">Previous Section</A> <A HREF="ch04.1.htm">Next page</A></P><H1>Section 4</H1><H1><A NAME="pgfId=524"></A>Expressions</H1><P><P CLASS="Body"><A NAME="pgfId=525"></A>This section describes the operatorsand operands available in the Verilog HDL, and how to use them to form expressions.</P><P><P CLASS="Body"><A NAME="pgfId=547"></A>An <I>expression</I> is a constructthat combines <I>operands</I> with <I>operators</I> to produce a resultthat is a function of the values of the operands and the semantic meaningof the operator. Any legal operand, such as a net bit-select, without anyoperator is considered an expression. Wherever a value is needed in a VerilogHDL statement, an expression can be used.</P><P><P CLASS="Body"><A NAME="pgfId=580"></A>Some statement constructs requirean expression to be a <I>constant expression</I> . The operands of a constantexpression consists of constant numbers and predefined parameter names only,but can use any of the operators defined in Table 4-1.</P><P><P CLASS="Body"><A NAME="pgfId=527"></A>A <I>scalar expression</I> isan expression that evaluates to a scalar (single bit) result. If the expressionevaluates to a vector (multi-bit) result, then the least significant bitof the result is used as the scalar result.</P><P><P CLASS="Body"><A NAME="pgfId=526"></A>The data types <B>integer</B>, <B>time</B> , <B>real</B> , and <B>realtime</B> share the same traitsas the data type <B>reg</B> when used in expressions. Descriptions pertainingto register usage apply to variables of these types as well.</P><P><P CLASS="Body"><A NAME="pgfId=528"></A>An <I>operand</I> can be oneof the following:</P><UL> <LI><A NAME="pgfId=529"></A>constant number (including real) <LI><A NAME="pgfId=895"></A>net <LI><A NAME="pgfId=531"></A>register variables of type reg, integer, time, real, and realtime <LI><A NAME="pgfId=532"></A>net bit-select <LI><A NAME="pgfId=533"></A>bit-select of type reg, integer, and time <LI><A NAME="pgfId=534"></A>net part-select <LI><A NAME="pgfId=535"></A>part-select of type reg, integer, and time <LI><A NAME="pgfId=536"></A>memory element <LI><A NAME="pgfId=537"></A>a call to a user-defined function or system defined function that returns any of the above</UL><P><A HREF="ch04.1.htm#pgfId=539" CLASS="Hypertext">4.1 Operators </A></P><P><A HREF="ch04.2.htm#pgfId=626" CLASS="Hypertext">4.2 Operands </A></P><P><A HREF="ch04.3.htm#pgfId=732" CLASS="Hypertext">4.3 Minimum, typical,maximum delay expressions</A></P><P><A HREF="ch04.4.htm#pgfId=749" CLASS="Hypertext">4.4 Expression bit lengths</A></P><P><HR ALIGN="LEFT"></P><P><A HREF="../../../Verilog.htm">Back to Verilog LRM index</A> <A HREF="ch04.htm">Next Section (disabled)</A> <A HREF="../03/ch03.htm">Previous Section</A> <A HREF="ch04.1.htm">Next page</A></BODY></HTML>⌨️ 快捷键说明
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