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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch13.css"><TITLE> Section 13</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="none">Chapter start</A> <A HREF="ch13.1.htm">Next page</A></P></DIV><DIV><H1 CLASS="Chapter"><A NAME="pgfId=301"> </A>Section 13<A NAME="68732"> </A></H1><H1 CLASS="ChapterTitle"><A NAME="pgfId=406"> </A><A NAME="57786"> </A><A NAME="marker=22"> </A>Specify blocks</H1><P CLASS="Body"><A NAME="pgfId=407"> </A>Two types of HDL constructs are often used to describe <A NAME="marker=69"> </A>delays for structural models such as ASIC cells. They are:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=392"> </A><I CLASS="Emphasis">distributed delays</I><A NAME="marker=74"> </A>, which specify the time it takes events to propagate through gates and nets inside the module (<A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/13/ch07.htm#56851" CLASS="XRef"></A>).</LI><LI CLASS="DashedList"><A NAME="pgfId=408"> </A><I CLASS="Emphasis">module path delays</I>, which describe the time it takes an event at a source (input port or inout port) to propagate to a destination (output port or inout port). </LI></UL><P CLASS="Body"><A NAME="pgfId=309"> </A>This section describes how paths are specified in a module and how delays are assigned to these paths. </P><H2 CLASS="SectionTOC"><A HREF="ch13.1.htm#pgfId=517" CLASS="Hypertext">13.1 Specify Block Declaration</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.2.htm#pgfId=422" CLASS="Hypertext">13.2 Declaring parameters in specify blocks</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.3.htm#pgfId=435" CLASS="Hypertext">13.3 Module path declarations</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.4.htm#pgfId=512" CLASS="Hypertext">13.4 Assigning delays to module paths</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.5.htm#pgfId=307" CLASS="Hypertext">13.5 Mixing module path delays and distributed delays</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.6.htm#pgfId=628" CLASS="Hypertext">13.6 Driving wired logic</A></H2><H2 CLASS="SectionTOC"><A HREF="ch13.7.htm#pgfId=709" CLASS="Hypertext">13.7 Controlling pulses on module paths with PATHPULSE$</A></H2></DIV><HR><P><A HREF="none">Chapter start</A> <A HREF="ch13.1.htm">Next page</A></P></BODY></HTML>⌨️ 快捷键说明
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