ch13.3.htm

Verilog DHL教程

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Table&nbsp;13-2: List of valid operators in state dependent path delay expression</P>
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operator</P>
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description</P>
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operator</P>
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description</P>
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<TD ROWSPAN="1" COLSPAN="1">
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~</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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bit-wise negation</P>
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&amp;</P>
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<TD ROWSPAN="1" COLSPAN="1">
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reduction and</P>
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&amp;</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=532">
 </A>
bit-wise and</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=533">
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| </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=534">
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reduction or</P>
</TD>
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<A NAME="pgfId=535">
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|</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=536">
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bit-wise or</P>
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<A NAME="pgfId=537">
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^</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=538">
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reduction xor</P>
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<TD ROWSPAN="1" COLSPAN="1">
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^</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=540">
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bit-wise xor</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=541">
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~&amp;</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=547">
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reduction nand</P>
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<TD ROWSPAN="1" COLSPAN="1">
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^~ ~^</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=558">
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bit-wise xnor</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=559">
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~|</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=560">
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reduction nor</P>
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<TD ROWSPAN="1" COLSPAN="1">
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==</P>
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<TD ROWSPAN="1" COLSPAN="1">
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logical equality</P>
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<TD ROWSPAN="1" COLSPAN="1">
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<A NAME="pgfId=563">
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^~ ~^</P>
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<A NAME="pgfId=564">
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reduction xnor</P>
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!=</P>
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logical inequality</P>
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{}</P>
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concatenation</P>
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&amp;&amp;</P>
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logical and</P>
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{ {} }</P>
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replication</P>
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||</P>
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logical or</P>
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?:</P>
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conditional</P>
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!</P>
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logical not</P>
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</P>
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<P CLASS="Body">
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A conditional expression shall evaluate to true (<CODE CLASS="code">
1</CODE>
) for the state-dependent path to be assigned a delay value. If the conditional expression evaluates to <CODE CLASS="code">
x</CODE>
 or <CODE CLASS="code">
z</CODE>
, it shall be treated as true. If the conditional expression evaluates to multiple bits, the least significant bit shall represent the result. The conditional expression can have any number of operands and operators.</P>
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Simple state-dependent paths</P>
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If the path description of a state-dependent path is a simple path, then it is called a <I CLASS="Emphasis">
simple state-dependent path</I>
. The simple path description is discussed in <A HREF="ch13.3.htm#describing module paths (&amp; rules)" CLASS="XRef">
See Simple module paths</A>
.</P>
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<DIV>
<H3 CLASS="Example">
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The following example uses state-dependent paths to describe the timing of an XOR gate.</P>
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</P>
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In this example, first two state-dependent paths describe a pair of output rise and fall delay times when the XOR gate (<CODE CLASS="code">
x1</CODE>
) inverts a changing input. The last two state-dependent paths describe another pair of output rise and fall delay times when the XOR gate buffers a changing input.</P>
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The example below models a partial ALU. The state-dependent paths specify different delays for different ALU operations.</P>
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In the preceding example, the first three path declarations declare paths extending from operand inputs <CODE CLASS="code">
i1</CODE>
 and <CODE CLASS="code">
i2</CODE>
 to the <CODE CLASS="code">
o1</CODE>
 output. The delays on these paths are assigned to operations on the basis of the operation specified by the inputs on <CODE CLASS="code">
opcode</CODE>
. The last path declaration declares a path from the <CODE CLASS="code">
opcode</CODE>
 input to the <CODE CLASS="code">
o1</CODE>
 output.</P>
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Edge-sensitive state-dependent paths</P>
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If the path description of a state-dependent path describes an edge-dependent path, then the state-dependent path is called an<I CLASS="Emphasis">
 edge-sensitive state-dependent path</I>
. The edge-sensitive paths are discussed in <A HREF="ch13.3.htm#14683" CLASS="XRef">
See Edge-sensitive paths</A>
.</P>
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Different delays can be assigned to the same edge-sensitive path as long as the following criteria are met:</P>
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The edge, condition, or both make each declaration unique.</LI>
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The port is referenced in the same way in all path declarations (entire port, bit-select, or part-select).</LI>
</UL>
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<DIV>
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In this example, if the positive edge of <CODE CLASS="code">
clock</CODE>
 occurs when <CODE CLASS="code">
reset</CODE>
 and <CODE CLASS="code">
clear</CODE>
 are low, a module path extends from <CODE CLASS="code">
clock</CODE>
 to <CODE CLASS="code">
out</CODE>
 using a rise delay of 10 and a fall delay of 8.</P>
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