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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch13.css"><TITLE> 13.3 Module path declarations</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="ch13.htm">Chapter start</A> <A HREF="ch13.2.htm">Previous page</A> <A HREF="ch13.4.htm">Next page</A></P></DIV><H1 CLASS="Section"><A NAME="pgfId=435"> </A>13.3 <A NAME="45352"> </A>Module path declarations</H1><P CLASS="Body"><A NAME="pgfId=437"> </A>There are two steps required to set up module path delays in a specify block:</P><OL><P CLASS="NumberedLista"><A NAME="pgfId=312"> </A>a) describe the module paths</P><P CLASS="NumberedListb"><A NAME="pgfId=334"> </A>b) assign delays to those paths (<A HREF="ch13.4.htm#27453" CLASS="XRef">See Assigning delays to module paths</A>)</P></OL><P CLASS="Body"><A NAME="pgfId=372"> </A>The syntax of the module path declaration is described below. </P><P CLASS="Body"><A NAME="pgfId=458"> </A></P><DIV><IMG SRC="ch13-5.gif"></DIV><P CLASS="BNFCapBody"><A NAME="pgfId=473"> </A>Syntax 13-3<A NAME="30112"> </A>: Syntax of the module path declaration</P><P CLASS="Body"><A NAME="pgfId=467"> </A>A module path may be described as a <I CLASS="Emphasis">simple path</I>, an <I CLASS="Emphasis">edge sensitive path</I>, or a <I CLASS="Emphasis">state dependent path</I>. A <A NAME="marker=138"> </A>module path shall be defined inside a specify block as a connection between a source signal and a destination signal. Module paths can connect any combination of vectors and scalars.</P><DIV><H3 CLASS="Example"><A NAME="pgfId=310"> </A></H3><P CLASS="Body"><A NAME="pgfId=335"> </A><A HREF="ch13.3.htm#path delays" CLASS="XRef">See : Module path delays</A> illustrates a circuit with module path delays. More than one source (<CODE CLASS="code">A</CODE>, <CODE CLASS="code">B</CODE>, <CODE CLASS="code">C</CODE>, and <CODE CLASS="code">D</CODE>) may have a module path to the same destination (<CODE CLASS="code">Q</CODE>), and different delays may be specified for each input to output path.</P><P CLASS="Body"><A NAME="pgfId=339"> </A></P><DIV><IMG SRC="ch13-6.gif"></DIV><P CLASS="FigCapBody"><A NAME="pgfId=340"> </A>Figure 13-1<A NAME="path delays"> </A>: Module path delays</P><P CLASS="SubSection"><A NAME="pgfId=304"> </A><A NAME="marker=84"> </A>Module path restrictions</P><P CLASS="Body"><A NAME="pgfId=346"> </A>Module paths have the following restrictions:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=468"> </A>The <A NAME="marker=89"> </A>module path source shall be a net that is connected to a module input port or inout port.</LI><LI CLASS="DashedList"><A NAME="pgfId=469"> </A>The <A NAME="marker=90"> </A>module path destination shall be a net or register that is connected to a module output port or inout port.</LI><LI CLASS="DashedList"><A NAME="pgfId=622"> </A>The module path destination shall have only one driver inside the module.</LI></UL><P CLASS="SubSection"><A NAME="pgfId=368"> </A><A NAME="marker=109"> </A>Simple module paths<A NAME="describing module paths (& rules)"> </A></P><P CLASS="Body"><A NAME="pgfId=414"> </A>The syntax for specifying a simple module path is as follows:</P><P CLASS="Body"><A NAME="pgfId=462"> </A></P><DIV><IMG SRC="ch13-7.gif"></DIV><P CLASS="BNFCapBody"><A NAME="pgfId=471"> </A>Syntax 13-4: Syntax for simple module path</P><P CLASS="Body"><A NAME="pgfId=476"> </A>Simple path can be declared in one of the two forms:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=495"> </A>source <CODE CLASS="code">*></CODE><A NAME="marker=117"> </A> destination</LI><LI CLASS="DashedList"><A NAME="pgfId=482"> </A>source<A NAME="marker=116"> </A> <CODE CLASS="code">=></CODE> destination </LI></UL><P CLASS="Body"><A NAME="pgfId=508"> </A>The symbols <CODE CLASS="code">*></CODE> and <CODE CLASS="code">=></CODE> each represent a different kind of connection between the module path source and the module path destination. The operator <CODE CLASS="code">*></CODE> establishes a <I CLASS="Emphasis">full connection</I> between source and destination. The operator <CODE CLASS="code">=></CODE> establishes a <I CLASS="Emphasis">parallel connection</I> between source and destination. Refer to <A HREF="ch13.3.htm#40926" CLASS="XRef">See Full connection and parallel connection paths</A> for a description of full connection and parallel connection paths.</P></DIV><DIV><H3 CLASS="Example"><A NAME="pgfId=359"> </A></H3><P CLASS="Body"><A NAME="pgfId=297"> </A>The following three examples illustrate valid simple module path declarations.</P><P CLASS="Body"><A NAME="pgfId=361"> </A></P><DIV><IMG SRC="ch13-8.gif"></DIV><P CLASS="SubSection"><A NAME="pgfId=290"> </A><A NAME="14683"> </A>Edge-sensitive paths <A NAME="marker=18"> </A><A NAME="marker=20"> </A><A NAME="marker=124"> </A><A NAME="marker=125"> </A></P><P CLASS="Body"><A NAME="pgfId=292"> </A>When a module path is described using an edge transition at the source, it is called an <I CLASS="Emphasis">edge-sensitive path</I>. The edge-sensitive path construct is used to model the timing of input to output delays which only occur when a specified edge occurs at the source signal.</P><P CLASS="Body"><A NAME="pgfId=299"> </A>The syntax of the edge-sensitive path declaration is shown below. </P><P CLASS="Body"><A NAME="pgfId=332"> </A></P><DIV><IMG SRC="ch13-9.gif"></DIV></DIV><DIV><H2 CLASS="BNFCapPage"><A NAME="pgfId=336"> </A><A NAME="89910"> </A>: Syntax of the edge-sensitive path declaration<A NAME="marker=132"> </A></H2><P CLASS="Body"><A NAME="pgfId=337"> </A>The edge identifier may be one of the keywords <B CLASS="Keyword">posedge</B> or <B CLASS="Keyword">negedge</B>, associated with an input terminal descriptor which may be any scalar input port or inout port, or bit-select of that port. If a vector port is specified as the input terminal descriptor, the edge transition shall be detected on the least significant bit. If the edge transition is not specified, the path shall be considered active on any transition at the input terminal.</P><P CLASS="Body"><A NAME="pgfId=338"> </A>An edge-sensitive path may be specified with full connections (<CODE CLASS="code">*></CODE>) or parallel connections (<CODE CLASS="code">=></CODE>). For parallel connections (<CODE CLASS="code">=></CODE>), the destination shall be any scalar output or inout port, or one of its bit-selects. For full connections (<CODE CLASS="code">*></CODE>), the destination shall be a list of one or more of the vector or scalar output and inout ports, and bit-selects or part-selects of those ports. Refer to <A HREF="ch13.3.htm#40926" CLASS="XRef">See Full connection and parallel connection paths</A> for a description of parallel paths and full connection paths.</P><P CLASS="Body"><A NAME="pgfId=342"> </A>The data source expression is an arbitrary expression, which serves as a description of the flow of data to the path destination. This arbitrary data path description does not affect the actual propagation of data or events through the model; how an event at the data path source propagates to the destination depends on the internal logic of the module. The polarity operator describes whether the data path is inverting or non-inverting.</P><DIV><H3 CLASS="Example"><A NAME="pgfId=347"> </A> <A NAME="marker=134"> </A></H3><P CLASS="Body"><A NAME="pgfId=349"> </A>1. The following example demonstrates an edge-sensitive path declaration with a positive polarity operator:</P><PRE CLASS="CodeIndent"><A NAME="pgfId=354"> </A>( <B CLASS="Keyword">posedge</B> clock => ( out +: in ) ) = (10, 8);</PRE><P CLASS="Body"><A NAME="pgfId=355"> </A>In this example, at the positive edge of <CODE CLASS="code">clock</CODE>, a module path extends from <CODE CLASS="code">clock</CODE> to <CODE CLASS="code">out</CODE> using a rise delay of 10 and a fall delay of 8. The data path is from <CODE CLASS="code">in</CODE> to <CODE CLASS="code">out</CODE>, and <CODE CLASS="code">in</CODE> is not inverted as it propagates to <CODE CLASS="code">out</CODE>.</P><P CLASS="Body"><A NAME="pgfId=343"> </A>2. The following example demonstrates an edge-sensitive path declaration with a negative polarity operator:</P><PRE CLASS="CodeIndent"><A NAME="pgfId=345"> </A>( <B CLASS="Keyword">negedge</B> clock[0] => ( out -: in ) ) = (10, 8);</PRE><P CLASS="Body"><A NAME="pgfId=621"> </A>In this example, at the negative edge of <CODE CLASS="code">clock[0]</CODE>, a module path extends from <CODE CLASS="code">clock[0]</CODE> to <CODE CLASS="code">out</CODE> using a rise delay of 10 and a fall delay of 8. The data path is from <CODE CLASS="code">in</CODE> to <CODE CLASS="code">out</CODE>, and <CODE CLASS="code">in</CODE> is inverted as it propagates to <CODE CLASS="code">out</CODE>.</P><P CLASS="Body"><A NAME="pgfId=356"> </A>3. The following example demonstrates an edge-sensitive path declaration with no edge identifier:</P><PRE CLASS="CodeIndent"><A NAME="pgfId=357"> </A>( clock => ( out : in ) ) = (10, 8); </PRE><P CLASS="Body"><A NAME="pgfId=358"> </A>In this example, at any change in <CODE CLASS="code">clock</CODE>, a module path extends from <CODE CLASS="code">clock</CODE> to <CODE CLASS="code">out</CODE>.</P><P CLASS="SubSection"><A NAME="pgfId=375"> </A><A NAME="24633"> </A>State<A NAME="marker=136"> </A>-dependent<A NAME="marker=137"> </A> paths</P><P CLASS="Body"><A NAME="pgfId=376"> </A>A <I CLASS="Emphasis">state-dependent path</I> makes it possible to assign a delay to a module path that affects signal propagation delay through the path only if specified conditions are true.</P><P CLASS="Body"><A NAME="pgfId=377"> </A>A state-dependent path description includes the following items:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=378"> </A>a conditional expression that, when evaluated true, enables the module path</LI><LI CLASS="DashedList"><A NAME="pgfId=440"> </A>a module path description</LI><LI CLASS="DashedList"><A NAME="pgfId=443"> </A>a delay expression that applies to the module path</LI></UL><P CLASS="Body"><A NAME="pgfId=451"> </A>The syntax for the state-dependent path declaration is shown below:</P><P CLASS="Body"><A NAME="pgfId=453"> </A></P><DIV><IMG SRC="ch13-10.gif"></DIV><P CLASS="BNFCapBody"><A NAME="pgfId=464"> </A>Syntax 13-6<A NAME=""> </A><A NAME="marker=144"> </A>: Syntax<A NAME="marker=145"> </A> of state-dependant paths</P><P CLASS="SubSubSect"><A NAME="pgfId=470"> </A>Conditional expression</P><P CLASS="Body"><A NAME="pgfId=474"> </A>The operands in the conditional expression shall be constructed from the following:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=475"> </A>scalar or vector module input ports or inout ports or their bit-select or part-select</LI><LI CLASS="DashedList"><A NAME="pgfId=477"> </A>compile time constants (constant numbers and specify parameters)</LI></UL><P CLASS="Body"><A NAME="pgfId=480"> </A>The following is a list of valid operators that may be used in conditional expressions:</P><P CLASS="Body"><A NAME="pgfId=592"> </A></P>⌨️ 快捷键说明
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