ch07.f.htm

Verilog DHL教程

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min(d1, d2)</P>
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d3</P>
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z</P>
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0</P>
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d2</P>
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d2</P>
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z</P>
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1</P>
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d1</P>
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d1</P>
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z</P>
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x</P>
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min(d1, d2)	</P>
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min(d1, d2, d3)</P>
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<DIV>
<H2 CLASS="Example">
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</H2>
<P CLASS="Body">
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1. The following is an example of a delay specification with one, two, and three delays:</P>
<PRE CLASS="CodeIndent"><A NAME="pgfId=1047"> </A>
<B CLASS="Keyword">and</B>
 #(10) a1 (out, in1, in2);													// Only one delay</PRE>
<PRE CLASS="CodeIndent"><A NAME="pgfId=1049"> </A>
<B CLASS="Keyword">and</B>
 #(10,12) a2 (out, in1, in2);													// rise and fall delays</PRE>
<PRE CLASS="CodeIndent"><A NAME="pgfId=1052"> </A>
<B CLASS="Keyword">bufif0</B>
 #(10,12,11) b3 (out, in, ctrl);													// rise, fall, and turn-off delays</PRE>
<P CLASS="Body">
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4. The following <A NAME="marker=610">
 </A>
example specifies a simple latch module with tri-state outputs, where individual delays are given to the gates. The propagation delay from the primary inputs to the outputs of the module will be cumulative, and depends on the signal path through the network.</P>
<P CLASS="Body">
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</P>
<DIV>
<IMG SRC="ch07-35.gif">
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<P CLASS="SubSection">
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<A NAME="marker=613">
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Min/typ/max delays</P>
<P CLASS="Body">
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The syntax for delays on gate primitives (including User-Defined Primitives, see <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/07/ch08.htm#68347" CLASS="XRef">
</A>
), nets, and continuous assignments shall allow three values each for the <A NAME="marker=614">
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rising, <A NAME="marker=616">
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falling, and <A NAME="marker=618">
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turn-off delays. The minimum, typical, and maximum values for each delay shall be specified as constant expressions separated by colons. There shall be no required relation (e.g. min &#163; typ &#163; max) between the expressions for minimum, typical, and maximum delays. These can be any three constant expressions.</P>
</DIV>
<DIV>
<H2 CLASS="Example">
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</H2>
<P CLASS="Body">
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The following example shows <CODE CLASS="code">
min/typ/max</CODE>
 values for rising, falling, and turn-off delays:</P>
<P CLASS="Body">
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</P>
<DIV>
<IMG SRC="ch07-36.gif">
</DIV>
<P CLASS="Body">
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The syntax for delay controls in procedural statements (see <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/07/ch09.htm#39185" CLASS="XRef">
</A>
) also allows minimum, typical, and maximum values. These are specified by expressions separated by colons. The following example illustrates this concept.</P>
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</P>
<DIV>
<IMG SRC="ch07-37.gif">
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<P CLASS="SubSection">
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<A NAME="97621">
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Trireg net charge decay<A NAME="marker=623">
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</P>
<P CLASS="Body">
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Like all nets, the delay specification in a <B CLASS="Keyword">
trireg</B>
 net declaration can contain up to three delays. The first two delays shall specify the delay for transition to the <CODE CLASS="code">
1</CODE>
 and <CODE CLASS="code">
0</CODE>
 logic states when the <B CLASS="Keyword">
trireg</B>
 net is driven to these states by a driver. The third delay shall specify the <I CLASS="Emphasis">
charge decay time</I>
 instead of the delay in a transition to the <CODE CLASS="code">
z</CODE>
 logic state. The charge decay time specifies the delay between when a <B CLASS="Keyword">
trireg</B>
 net's drivers turn off and when its stored charge can no longer be determined.</P>
<P CLASS="Body">
<A NAME="pgfId=1671">
 </A>
A <B CLASS="Keyword">
trireg</B>
 net does not need turn-off delay specification because a <B CLASS="Keyword">
trireg</B>
 net never makes a transition to the <CODE CLASS="code">
z</CODE>
 logic state. When a <B CLASS="Keyword">
trireg</B>
 net's drivers make transitions from the <CODE CLASS="code">
1</CODE>
, <CODE CLASS="code">
0</CODE>
, or <CODE CLASS="code">
x</CODE>
 logic states to off, the <B CLASS="Keyword">
trireg</B>
 net shall retain the previous <CODE CLASS="code">
1</CODE>
, <CODE CLASS="code">
0</CODE>
, or <CODE CLASS="code">
x</CODE>
 logic state that was on its drivers. The <CODE CLASS="code">
z</CODE>
 value shall not propagate from a <B CLASS="Keyword">
trireg</B>
 net's drivers to a <B CLASS="Keyword">
trireg</B>
 net. A <B CLASS="Keyword">
trireg</B>
 net can only hold a <CODE CLASS="code">
z</CODE>
 logic state when <CODE CLASS="code">
z</CODE>
 is the <B CLASS="Keyword">
trireg</B>
 net's initial logic state or when it is forced to the <CODE CLASS="code">
z</CODE>
 state with a <B CLASS="Keyword">
force</B>
 statement (see <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/07/ch09.htm#22168" CLASS="XRef">
</A>
).</P>
<P CLASS="Body">
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A delay specification for charge decay models a charge storage node that is not ideal--a charge storage node whose charge leaks out through its surrounding devices and connections.</P>
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The following subsections describe the charge decay process and the delay specification for charge decay.</P>
<P CLASS="SubSubSect">
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The charge decay process</P>
<P CLASS="Body">
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Charge decay is the cause of transition of a 1 or 0 that is stored in a <B CLASS="Keyword">
trireg</B>
 net to an unknown value (<CODE CLASS="code">
x</CODE>
) after a specified delay. The charge decay process shall begin when the <B CLASS="Keyword">
trireg</B>
 net's drivers turn off and the <B CLASS="Keyword">
trireg</B>
 net starts to hold charge. The charge decay process shall end under the following two conditions:</P>
<OL>
<P CLASS="NumberedLista">
<A NAME="pgfId=1676">
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a)	The delay specified by charge decay time elapses and the <B CLASS="Keyword">
trireg</B>
 net makes a transition from <CODE CLASS="code">
1</CODE>
 or <CODE CLASS="code">
0</CODE>
 to <CODE CLASS="code">
x</CODE>
.</P>
<P CLASS="NumberedListb">
<A NAME="pgfId=1677">
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b)	The <B CLASS="Keyword">
trireg</B>
 net's drivers turn on and propagate a <CODE CLASS="code">
1</CODE>
, <CODE CLASS="code">
0</CODE>
 or <CODE CLASS="code">
x</CODE>
 into the <B CLASS="Keyword">
trireg</B>
 net.</P>
</OL>
<P CLASS="SubSubSect">
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The delay specification for charge decay time<A NAME="marker=624">
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</P>
<P CLASS="Body">
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The third delay in a <B CLASS="Keyword">
trireg</B>
 net declaration shall specify the charge decay time. A three-valued delay specification in a <B CLASS="Keyword">
trireg</B>
 net declaration shall have the following form:</P>
<PRE CLASS="CodeIndent"><A NAME="pgfId=1680"> </A>
#(d1,&nbsp;d2,&nbsp;d3)							// (rise_delay, fall_delay, charge_decay_time)</PRE>
<P CLASS="Body">
<A NAME="pgfId=1681">
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The charge decay time specification in a <B CLASS="Keyword">
trireg</B>
 net declaration shall be preceded by a rise and a fall delay specification. </P>
</DIV>
<DIV>
<H2 CLASS="Example">
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 </A>
</H2>
<P CLASS="Body">
<A NAME="pgfId=1056">
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The following example shows a specification of the charge decay time in a <B CLASS="Keyword">
trireg</B>
 net declaration:</P>
<PRE CLASS="CodeIndent"><A NAME="pgfId=1682"> </A>
<B CLASS="Keyword">trireg</B>
 (<B CLASS="Keyword">large</B>
) #(0,0,50) cap1;</PRE>
<P CLASS="Body">
<A NAME="pgfId=1683">
 </A>
This example declares a <B CLASS="Keyword">
trireg</B>
 net named <CODE CLASS="code">
cap1</CODE>
. This <B CLASS="Keyword">
trireg</B>
 net stores a <B CLASS="Keyword">
large</B>
 charge. The delay specifications for the rise delay is 0, the fall delay is 0, and the charge decay time specification is 50 time units.</P>
<P CLASS="Body">
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2. Next example presents a source description file that contains a <B CLASS="Keyword">
trireg</B>
 net declaration with a charge decay time specification. <A HREF="ch07.f.htm#47134" CLASS="XRef">
See : Trireg net with capacitance</A>
 shows an equivalent schematic for the source description.</P>
<P CLASS="Body">
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</P>
<DIV>
<IMG SRC="ch07-38.gif">
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<P CLASS="FigCapBody">
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Figure&nbsp;7-26<A NAME="47134">
 </A>
: Trireg net with capacitance</P>
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<DIV>
<IMG SRC="ch07-39.gif">
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<P CLASS="Body">
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</P>
</DIV>
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