📄 ch07.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch07.css"><TITLE> Section 7</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="none">Chapter start</A> <A HREF="ch07.1.htm">Next page</A></P></DIV><DIV><H1 CLASS="Chapter"><A NAME="pgfId=1402"> </A>Section 7<A NAME="36723"> </A></H1><H1 CLASS="ChapterTitle"><A NAME="pgfId=1403"> </A><A NAME="34276"> </A><A NAME="marker=105"> </A>Gate and switch level modeling</H1><P CLASS="Body"><A NAME="pgfId=1016"> </A>This section describes the syntax and semantics of these built-in primitives and how a hardware design can be described using these primitives.</P><P CLASS="Body"><A NAME="pgfId=1162"> </A>There are 14 logic gates and 12 switches pre-defined in Verilog HDL to provide <I CLASS="Emphasis">gate</I> and <I CLASS="Emphasis">switch</I> level modeling facility. Modeling with <A NAME="marker=110"> </A>logic <A NAME="marker=111"> </A>gates and switches has the following advantages:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=1405"> </A>Gates provide a much closer one to one mapping between the actual circuit and the model.</LI><LI CLASS="DashedList"><A NAME="pgfId=1406"> </A>There is no continuous assignment equivalent to the bidirectional transfer gate.</LI></UL><H2 CLASS="SectionTOC"><A HREF="ch07.1.htm#pgfId=1189" CLASS="Hypertext">7.1 Gate and switch declaration syntax </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.2.htm#pgfId=1465" CLASS="Hypertext">7.2 And, nand, nor, or, xor, and xnor gates </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.3.htm#pgfId=1476" CLASS="Hypertext">7.3 Buf and not gates </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.4.htm#pgfId=1485" CLASS="Hypertext">7.4 Bufif1, bufif0, notif1, and notif0 gates </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.5.htm#pgfId=1496" CLASS="Hypertext">7.5 MOS switches</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.6.htm#pgfId=1506" CLASS="Hypertext">7.6 Bidirectional pass switches</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.7.htm#pgfId=1513" CLASS="Hypertext">7.7 Cmos switches</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.8.htm#pgfId=1519" CLASS="Hypertext">7.8 Pullup and pulldown sources</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.9.htm#pgfId=1525" CLASS="Hypertext">7.9 Implicit net declarations </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.a.htm#pgfId=1531" CLASS="Hypertext">7.10 Logic strength modeling </A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.b.htm#pgfId=1550" CLASS="Hypertext">7.11 Strengths and values of combined signals</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.c.htm#pgfId=1641" CLASS="Hypertext">7.12 <EM CLASS="-"></EM>Strength reduction by non-resistive devices</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.d.htm#pgfId=1644" CLASS="Hypertext">7.13 Strength reduction by resistive devices</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.e.htm#pgfId=1646" CLASS="Hypertext">7.14 Strengths of net types</A></H2><H2 CLASS="SectionTOC"><A HREF="ch07.f.htm#pgfId=1653" CLASS="Hypertext">7.15 Gate and net delays </A></H2></DIV><HR><P><A HREF="none">Chapter start</A> <A HREF="ch07.1.htm">Next page</A></P></BODY></HTML>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -