ch03.htm

来自「Verilog DHL教程」· HTM 代码 · 共 55 行

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<HTML><HEAD>  <META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac">  <LINK REL="STYLESHEET" HREF="ch03.css">  <TITLE> Section 3</TITLE></HEAD><BODY BGCOLOR="#ffffff"><P><A NAME="pgfId=369"></A><HR ALIGN=LEFT></P><P><A HREF="../../../Verilog.htm">Back&nbsp;&nbsp;to&nbsp;&nbsp;Verilog&nbsp;&nbsp;LRM&nbsp;&nbsp;index</A>&nbsp;&nbsp;&nbsp;<AHREF="../04/ch04.htm">Next&nbsp;&nbsp;Section</A>&nbsp;&nbsp;&nbsp;<A HREF="../02/ch02.htm">Previous&nbsp;&nbsp;Section</A>&nbsp;&nbsp;<A HREF="ch03.1.htm">Next&nbsp;&nbsp;page</A></P><H1>Section 3</H1><H1><A NAME="pgfId=398"></A>Data types</H1><P><P CLASS="Body"><A NAME="pgfId=399"></A>The set of Verilog HDL data typesis designed to represent the data storage and transmission elements foundin digital hardware.</P><P><A HREF="ch03.1.htm#pgfId=401" CLASS="Hypertext">3.1 Value set </A></P><P><A HREF="ch03.2.htm#pgfId=409" CLASS="Hypertext">3.2 Nets and registers</A></P><P><A HREF="ch03.3.htm#pgfId=434" CLASS="Hypertext">3.3 Vectors </A></P><P><A HREF="ch03.4.htm#pgfId=452" CLASS="Hypertext">3.4 Strengths</A></P><P><A HREF="ch03.5.htm#pgfId=473" CLASS="Hypertext">3.5 Implicit declarations</A></P><P><A HREF="ch03.6.htm#pgfId=478" CLASS="Hypertext">3.6 Net initialization</A></P><P><A HREF="ch03.7.htm#pgfId=366" CLASS="Hypertext">3.7 Net types </A></P><P><A HREF="ch03.8.htm#pgfId=536" CLASS="Hypertext">3.8 Memories </A></P><P><A HREF="ch03.9.htm#pgfId=552" CLASS="Hypertext">3.9 Integers, reals,times and realtimes</A></P><P><A HREF="ch03.a.htm#pgfId=588" CLASS="Hypertext">3.10 Parameters </A></P><P><A HREF="ch03.b.htm#pgfId=612" CLASS="Hypertext">3.11 Name spaces</A></P><P><HR ALIGN=LEFT></P><P><A HREF="../../../Verilog.htm">Back&nbsp;&nbsp;to&nbsp;&nbsp;Verilog&nbsp;&nbsp;LRM&nbsp;&nbsp;index</A>&nbsp;&nbsp;<AHREF="../04/ch04.htm">Next&nbsp;&nbsp;Section</A>&nbsp;&nbsp;<A HREF="../02/ch02.htm">Previous&nbsp;&nbsp;Section</A>&nbsp;&nbsp;&nbsp;<AHREF="ch03.1.htm">Next&nbsp;&nbsp;page</A></BODY></HTML>

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