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<HTML><HEAD> <META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac"> <LINK REL="STYLESHEET" HREF="ch03.css"> <TITLE> 3.1 Value set </TITLE></HEAD><BODY BGCOLOR="#ffffff"><P><A NAME="pgfId=401"></A><HR ALIGN=LEFT></P><P><A HREF="ch03.htm">Chapter start</A> <A HREF="ch03.htm">Previous page</A> <A HREF="ch03.2.htm">Next page</A></P><H1>3.1 Value set</H1><P><P CLASS="Body"><A NAME="pgfId=402"></A>The Verilog HDL value set consistsof four basic values:</P><PRE><A NAME="pgfId=403"></A> <CODE>0 </CODE>- represents a logic zero, or false condition<CODE>1 </CODE>- represents a logic one, or true condition<CODE>x</CODE> - represents an unknown logic value<CODE>z</CODE> - represents a high-impedance state</PRE><P><P CLASS="Body"><A NAME="pgfId=404"></A>The values <CODE>0</CODE> and<CODE>1</CODE> are logical complements of one another.</P><P><P CLASS="Body"><A NAME="pgfId=405"></A>When the <CODE>z</CODE> valueis present at the input of a gate, or when it is encountered in an expression,the effect is usually the same as an <CODE>x</CODE> value. Notable exceptionsare the MOS primitives, which can pass the <CODE>z</CODE> value.</P><P><P CLASS="Body"><A NAME="pgfId=406"></A>Almost all of the data typesin the Verilog HDL store all four basic values. The exceptions are the <I>event</I>type (see section 9.7.3), which has no storage, and the <B>trireg</B><CODE></CODE>net data type (see 3.7.3), which retains its first state when allof its drivers go to the high impedance value (<CODE> z</CODE> ). All bitsof vectors can be independently set to one of the four basic values.</P><P><P CLASS="Body"><A NAME="pgfId=407"></A>The language includes <I>strength</I>information in addition to the basic value information for net variables.This is described in detail in Section 7.</P><P><HR ALIGN=LEFT></P><P><A HREF="ch03.htm">Chapter start</A> <A HREF="ch03.htm">Previous page</A> <A HREF="ch03.2.htm">Next page</A></BODY></HTML>⌨️ 快捷键说明
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