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<HTML><HEAD> <META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac"> <TITLE>1.4 The contents of the language reference manual</TITLE></HEAD><BODY><P><A NAME="anchor648127"></A><HR ALIGN=LEFT></P><P><A HREF="ch01.htm">Chapter start</A> <A HREF="ch01.3.htm">Previous page</A> <A HREF="ch01.5.htm">Next page</A></P><H2>1.4 The contents of the language reference manual</H2><P><P CLASS="Body"><A NAME="pgfId=79"></A>A synopsis of these sections andannexes is presented here:</P><OL> <P><P CLASS="NumberedList1"><A NAME="pgfId=95"></A>1) <B>Introduction<BR> </B>This section discusses the conventions used in the document and the contents of the language reference manual. <P><P CLASS="NumberedList2"><A NAME="pgfId=96"></A>2) <B>Lexical conventions<BR> </B>This section describes how to specify and interpret the lexical tokens. <P><P CLASS="NumberedList2"><A NAME="pgfId=97"></A>3) <B>Data types<BR> </B>This section describes net and reg data types. This section also discusses the parameter data type for constant values and describes drive and charge strength of the values on nets. <P><P CLASS="NumberedList2"><A NAME="pgfId=98"></A>4) <B>Expressions<BR> </B>This section describes the operators and operands that can be used in expressions. <P><P CLASS="NumberedList2"><A NAME="pgfId=132"></A>5) <B>Scheduling semantics<BR> </B>This section describes the scheduling semantics of Verilog HDL. <P><P CLASS="NumberedList2"><A NAME="pgfId=99"></A>6) <B>Assignments<BR> </B>This section compares the two main types of assignment statements in the Verilog HDL--continuous assignments and procedural assignments. It describes the continuous assignment statement that drives values onto nets. <P><P CLASS="NumberedList2"><A NAME="pgfId=100"></A>7) <B>Gate and switch level modeling<BR> </B>This section describes the gate and switch level primitives and logic strength modeling. <P><P CLASS="NumberedList2"><A NAME="pgfId=101"></A>8) <B>User-defined primitives (UDPs)<BR> </B>This section describes how a primitive can be defined in the Verilog HDL and how these primitives are included in Verilog HDL models. <P><P CLASS="NumberedList2"><A NAME="pgfId=102"></A>9) <B>Behavioral modeling<BR> </B>This section describes procedural assignments, procedural continuous assignments and the behavioral language statements. <P><P CLASS="NumberedList2"><A NAME="pgfId=65"></A>10) <B>Tasks and functions<BR> </B>This section describes tasks and functions--procedures that can be called from more than one place in a behavioral model. It describes how tasks can be used like subroutines and how functions can be used to define new operators. <P><P CLASS="NumberedList2"><A NAME="pgfId=70"></A>11) <B>Disabling of named blocks and tasks<BR> </B>This section describes how to disable the execution of a task and a block of statements that has a specified name. <P><P CLASS="NumberedList2"><A NAME="pgfId=106"></A>12) <B>Hierarchical structures<BR> </B>This section describes how hierarchies are created in the Verilog HDL and how parameter values declared in a module can be overridden. <P><P CLASS="NumberedList2"><A NAME="pgfId=81"></A>13) <B>Specify blocks<BR> </B>This section describes how to specify timing relationships between input and output ports of a module. <P><P CLASS="NumberedList2"><A NAME="pgfId=52"></A>14) <B>System tasks and functions<BR> </B>This section describes the system tasks and functions. <P><P CLASS="NumberedList2"><A NAME="pgfId=133"></A>15) <B>Value change dump (VCD) file<BR> </B>This section describes the system tasks associated with Value Change Dump (VCD) file, and the format of the file. <P><P CLASS="NumberedList2"><A NAME="pgfId=50"></A>16) <B>Compiler directives<BR> </B>This section describes the compiler directives. <P><P CLASS="NumberedList2"><A NAME="pgfId=66"></A>17) <B>PLI interface mechanism<BR> </B>This section describes the interface mechanism which provides a means for users to link PLI task/function routine and access routine applications to Verilog software tools. <P><P CLASS="NumberedList2"><A NAME="pgfId=88"></A>18) <B>Using access routines<BR> </B>This section describes the access routines, with a general discussion of how and why to use them. <P><P CLASS="NumberedList2"><A NAME="pgfId=49"></A>19) <B>Access routine definitions</B> <BR> This section describes access routines, explaining their function, syntax, and usage. <P><P CLASS="NumberedList2"><A NAME="pgfId=89"></A>20) <B>Using task/function routines<BR> </B>This section provides an overview of the types of operations which are done with the task/function routines. <P><P CLASS="NumberedList2"><A NAME="pgfId=104"></A>21) <B>Task/function routine definitions<BR> </B>This section describes the task/function routines, explaining their function, syntax, and usage. <P><P CLASS="NumberedList2"><A NAME="pgfId=137"></A>22) <B>Using VPI routines<BR> </B>This section provides an overview of the types of operations which are done with the VPI routines. <P><P CLASS="NumberedList2"><A NAME="pgfId=105"></A>23) <B>VPI routine definitions<BR> </B>This section describes the Verilog Programming Interface (VPI) routines. <P><P CLASS="NumberedLista1"><A NAME="pgfId=82"></A>a) <B>Formal Syntax Definition<BR> </B>This annex describes, in the Backus-Naur Format (BNF), the syntax of the Verilog HDL. <P><P CLASS="NumberedListb1"><A NAME="pgfId=112"></A>b) <B>List of Keywords<BR> </B>This annex lists the Verilog HDL keywords. <P><P CLASS="NumberedListb1"><A NAME="pgfId=71"></A>c) <B>System Tasks and Functions (Informative)<BR> </B>This annex describes system tasks and functions that are frequently used, but are not part of the standard. <P><P CLASS="NumberedListb1"><A NAME="pgfId=93"></A>d) <B>Compiler Directives (Informative)<BR> </B>This annex describes compiler directives that are frequently used, but are not part of the standard. <P><P CLASS="NumberedListb1"><A NAME="pgfId=107"></A>e) <B>The acc_user.h file<BR> </B>This annex provides a listing of the contents of <CODE>acc_user.h</CODE> file. <P><P CLASS="NumberedListb1"><A NAME="pgfId=109"></A>f) <B>The veriuser.h file<BR> </B>This annex provides a listing of the contents of <CODE>veriuser.h</CODE> file. <P><P CLASS="NumberedListb1"><A NAME="pgfId=110"></A>g) <B>The vpi_user.h file<BR> </B>This annex provides a listing of the contents of <CODE>vpi_user.h</CODE> file.</OL><P><A HREF="ch01.htm">Chapter start</A> <A HREF="ch01.3.htm">Previous page</A> <A HREF="ch01.5.htm">Next page</A></BODY></HTML>⌨️ 快捷键说明
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