prev_cmp_mc8051_test.map.qmsg

mc8051源码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "comb_divider_rtl.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file comb_divider_rtl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 comb_divider-rtl " "Info: Found design unit 1: comb_divider-rtl" {  } { { "comb_divider_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/comb_divider_rtl.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "comb_divider_.vhd 1 1 " "Info: Found 1 design units, including 1 entities, in source file comb_divider_.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 comb_divider " "Info: Found entity 1: comb_divider" {  } { { "comb_divider_.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/comb_divider_.vhd" 72 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alumux_rtl.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file alumux_rtl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alumux-rtl " "Info: Found design unit 1: alumux-rtl" {  } { { "alumux_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alumux_rtl.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alumux_.vhd 1 1 " "Info: Found 1 design units, including 1 entities, in source file alumux_.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 alumux " "Info: Found entity 1: alumux" {  } { { "alumux_.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alumux_.vhd" 74 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alucore_rtl.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file alucore_rtl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alucore-rtl " "Info: Found design unit 1: alucore-rtl" {  } { { "alucore_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alucore_rtl.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alucore_.vhd 1 1 " "Info: Found 1 design units, including 1 entities, in source file alucore_.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 alucore " "Info: Found entity 1: alucore" {  } { { "alucore_.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alucore_.vhd" 73 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addsub_ovcy_rtl.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file addsub_ovcy_rtl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addsub_ovcy-rtl " "Info: Found design unit 1: addsub_ovcy-rtl" {  } { { "addsub_ovcy_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/addsub_ovcy_rtl.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addsub_ovcy_.vhd 1 1 " "Info: Found 1 design units, including 1 entities, in source file addsub_ovcy_.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 addsub_ovcy " "Info: Found entity 1: addsub_ovcy" {  } { { "addsub_ovcy_.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/addsub_ovcy_.vhd" 72 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addsub_cy_rtl.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file addsub_cy_rtl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addsub_cy-rtl " "Info: Found design unit 1: addsub_cy-rtl" {  } { { "addsub_cy_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/addsub_cy_rtl.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addsub_cy_.vhd 1 1 " "Info: Found 1 design units, including 1 entities, in source file addsub_cy_.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 addsub_cy " "Info: Found entity 1: addsub_cy" {  } { { "addsub_cy_.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/addsub_cy_.vhd" 72 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addsub_core_struc.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file addsub_core_struc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addsub_core-struc " "Info: Found design unit 1: addsub_core-struc" {  } { { "addsub_core_struc.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/addsub_core_struc.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mc8051_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file mc8051_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mc8051_test " "Info: Found entity 1: mc8051_test" {  } { { "mc8051_test.bdf" "" { Schematic "F:/quartusII_example/8051_test/8051_test/mc8051_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mc8051_test " "Info: Elaborating entity \"mc8051_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mc8051_core mc8051_core:inst " "Info: Elaborating entity \"mc8051_core\" for hierarchy \"mc8051_core:inst\"" {  } { { "mc8051_test.bdf" "inst" { Schematic "F:/quartusII_example/8051_test/8051_test/mc8051_test.bdf" { { 88 448 696 376 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mc8051_control mc8051_core:inst\|mc8051_control:i_mc8051_control " "Info: Elaborating entity \"mc8051_control\" for hierarchy \"mc8051_core:inst\|mc8051_control:i_mc8051_control\"" {  } { { "mc8051_core_struc.vhd" "i_mc8051_control" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_core_struc.vhd" 110 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_fsm mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_fsm:i_control_fsm " "Info: Elaborating entity \"control_fsm\" for hierarchy \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_fsm:i_control_fsm\"" {  } { { "mc8051_control_struc.vhd" "i_control_fsm" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_control_struc.vhd" 113 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_mem mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem " "Info: Elaborating entity \"control_mem\" for hierarchy \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\"" {  } { { "mc8051_control_struc.vhd" "i_control_mem" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_control_struc.vhd" 156 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mc8051_alu mc8051_core:inst\|mc8051_alu:i_mc8051_alu " "Info: Elaborating entity \"mc8051_alu\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\"" {  } { { "mc8051_core_struc.vhd" "i_mc8051_alu" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_core_struc.vhd" 163 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alumux mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|alumux:i_alumux " "Info: Elaborating entity \"alumux\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|alumux:i_alumux\"" {  } { { "mc8051_alu_struc.vhd" "i_alumux" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_alu_struc.vhd" 94 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "alumux_rtl.vhd(368) " "Warning (10037): Verilog HDL or VHDL warning at alumux_rtl.vhd(368): conditional expression evaluates to a constant" {  } { { "alumux_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alumux_rtl.vhd" 368 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "alumux_rtl.vhd(381) " "Warning (10037): Verilog HDL or VHDL warning at alumux_rtl.vhd(381): conditional expression evaluates to a constant" {  } { { "alumux_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alumux_rtl.vhd" 381 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "alumux_rtl.vhd(397) " "Warning (10037): Verilog HDL or VHDL warning at alumux_rtl.vhd(397): conditional expression evaluates to a constant" {  } { { "alumux_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/alumux_rtl.vhd" 397 0 0 } }  } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alucore mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|alucore:i_alucore " "Info: Elaborating entity \"alucore\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|alucore:i_alucore\"" {  } { { "mc8051_alu_struc.vhd" "i_alucore" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_alu_struc.vhd" 133 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addsub_core mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core " "Info: Elaborating entity \"addsub_core\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core\"" {  } { { "mc8051_alu_struc.vhd" "i_addsub_core" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_alu_struc.vhd" 144 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addsub_cy mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core\|addsub_cy:\\gen_greater_four:gen_addsub:4:gen_nibble_addsub:i_addsub_cy " "Info: Elaborating entity \"addsub_cy\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core\|addsub_cy:\\gen_greater_four:gen_addsub:4:gen_nibble_addsub:i_addsub_cy\"" {  } { { "addsub_core_struc.vhd" "\\gen_greater_four:gen_addsub:4:gen_nibble_addsub:i_addsub_cy" { Text "F:/quartusII_example/8051_test/8051_test/addsub_core_struc.vhd" 92 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addsub_ovcy mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core\|addsub_ovcy:\\gen_greater_four:gen_addsub:5:gen_last_addsub:i_addsub_ovcy " "Info: Elaborating entity \"addsub_ovcy\" for hierarchy \"mc8051_core:inst\|mc8051_alu:i_mc8051_alu\|addsub_core:i_addsub_core\|addsub_ovcy:\\gen_greater_four:gen_addsub:5:gen_last_addsub:i_addsub_ovcy\"" {  } { { "addsub_core_struc.vhd" "\\gen_greater_four:gen_addsub:5:gen_last_addsub:i_addsub_ovcy" { Text "F:/quartusII_example/8051_test/8051_test/addsub_core_struc.vhd" 103 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}