mc8051_test.map.qmsg

mc8051源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mc8051_rom mc8051_rom:inst1 " "Info: Elaborating entity \"mc8051_rom\" for hierarchy \"mc8051_rom:inst1\"" {  } { { "mc8051_test.bdf" "inst1" { Schematic "F:/quartusII_example/8051_test/8051_test/mc8051_test.bdf" { { 120 72 288 256 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mc8051_rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"mc8051_rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "mc8051_rom.v" "altsyncram_component" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_rom.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "mc8051_rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"mc8051_rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "mc8051_rom.v" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_rom.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ir21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ir21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ir21 " "Info: Found entity 1: altsyncram_ir21" {  } { { "db/altsyncram_ir21.tdf" "" { Text "F:/quartusII_example/8051_test/8051_test/db/altsyncram_ir21.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ir21 mc8051_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ir21:auto_generated " "Info: Elaborating entity \"altsyncram_ir21\" for hierarchy \"mc8051_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_ir21:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WMIO_MIO_BYTE_HEX_WORD_READ" "F:/quartusII_example/8051_test/8051_test/led.hex " "Warning: Byte addressed memory initialization file \"F:/quartusII_example/8051_test/8051_test/led.hex\" was read in the word-addressed format" {  } { { "F:/quartusII_example/8051_test/8051_test/led.hex" "" { Text "F:/quartusII_example/8051_test/8051_test/led.hex" 1 -1 0 } }  } 0 0 "Byte addressed memory initialization file \"%1!s!\" was read in the word-addressed format" 0 0 "" 0}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "4096 40 " "Critical Warning: Memory depth value (4096) in design file differs from memory depth value (40) in Memory Initialization File -- setting initial value for remaining addresses to 0" {  } { { "mc8051_rom.v" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_rom.v" 74 0 0 } }  } 1 0 "Memory depth value (%1!d!) in design file differs from memory depth value (%2!d!) in Memory Initialization File -- setting initial value for remaining addresses to 0" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff0 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff0\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 88 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff1 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff1\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 89 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff2 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t0ff2\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 90 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff0 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff0\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 91 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff1 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff1\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 92 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff2 data_in GND " "Warning (14130): Reduced register \"mc8051_core:inst\|mc8051_tmrctr:\\gen_mc8051_tmrctr:0:i_mc8051_tmrctr\|s_t1ff2\" with stuck data_in port to stuck value GND" {  } { { "mc8051_tmrctr_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd" 93 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[1\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[1\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[1\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[2\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[1\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[2\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[2\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[3\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[2\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[3\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[3\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[4\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[3\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[4\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[4\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[5\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[4\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[5\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[5\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[6\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[5\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[6\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[6\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[7\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[6\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[7\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[7\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p3\[7\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[1\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[1\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[1\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[2\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[1\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[2\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[2\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[3\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[2\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[3\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[3\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[4\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[3\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[4\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[4\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[5\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[4\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[5\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[5\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[6\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[5\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[6\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[6\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[7\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[6\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[7\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[7\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p2\[7\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[1\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[1\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[1\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[2\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[1\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[2\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[2\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[3\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[2\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[3\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[3\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[4\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[3\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[4\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[4\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[5\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[4\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[5\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[5\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[6\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[5\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[6\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[6\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[7\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[6\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[7\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[7\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p1\[7\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[1\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[1\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[1\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[2\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[1\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[2\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[2\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[3\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[2\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[3\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[3\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[4\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[3\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[4\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[4\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[5\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[4\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[5\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[5\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[6\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[5\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[6\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[6\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[7\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[6\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[7\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[7\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h1\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_p0\[7\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h1\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 715 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h1\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h1\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h1\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h1\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 493 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_tf1_h1\[0\] mc8051_core:inst\|mc8051_siu:\\gen_mc8051_siu:0:i_mc8051_siu\|s_ff0 " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_tf1_h1\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_siu:\\gen_mc8051_siu:0:i_mc8051_siu\|s_ff0\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 493 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_tf1_h2\[0\] mc8051_core:inst\|mc8051_siu:\\gen_mc8051_siu:0:i_mc8051_siu\|s_ff1 " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_tf1_h2\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_siu:\\gen_mc8051_siu:0:i_mc8051_siu\|s_ff1\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 493 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h2\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h2\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h2\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h2\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 493 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h3\[0\] mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h3\[0\] " "Info: Duplicate register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int1_h3\[0\]\" merged to single register \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|s_int0_h3\[0\]\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 493 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state 5 " "Info: State machine \"\|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state\" contains 5 states" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 88 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state " "Info: Selected Auto state machine encoding method for state machine \"\|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 88 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state " "Info: Encoding result for state machine \"\|mc8051_test\|mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec3 " "Info: Encoded state bit \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec3\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec2 " "Info: Encoded state bit \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec2\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd" 88 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec1 " "Info: Encoded state bit \"mc8051_core:inst\|mc8051_control:i_mc8051_control\|control_mem:i_control_mem\|state.exec1\"" {  } { { "control_mem_rtl.vhd" "" { Text "F:/qu