mc8051_test.map.rpt

mc8051源码

; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                          ;
+----------------------------------+-----------------+---------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                             ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+---------------------------------------+--------------------------------------------------------------------+
; led.hex                          ; yes             ; User Hexadecimal (Intel-Format) File  ; F:/quartusII_example/8051_test/8051_test/led.hex                   ;
; mc8051_rom.v                     ; yes             ; User Verilog HDL File                 ; F:/quartusII_example/8051_test/8051_test/mc8051_rom.v              ;
; mc8051_ramx.v                    ; yes             ; User Verilog HDL File                 ; F:/quartusII_example/8051_test/8051_test/mc8051_ramx.v             ;
; mc8051_ram.v                     ; yes             ; User Verilog HDL File                 ; F:/quartusII_example/8051_test/8051_test/mc8051_ram.v              ;
; addsub_core_.vhd                 ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/addsub_core_.vhd          ;
; mc8051_tmrctr_rtl.vhd            ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_rtl.vhd     ;
; mc8051_tmrctr_.vhd               ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_tmrctr_.vhd        ;
; mc8051_siu_rtl.vhd               ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_siu_rtl.vhd        ;
; mc8051_siu_.vhd                  ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_siu_.vhd           ;
; mc8051_p.vhd                     ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_p.vhd              ;
; mc8051_core_struc.vhd            ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_core_struc.vhd     ;
; mc8051_core.vhd                  ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_core.vhd           ;
; mc8051_control_struc.vhd         ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_control_struc.vhd  ;
; mc8051_control_.vhd              ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_control_.vhd       ;
; mc8051_alu_struc.vhd             ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_alu_struc.vhd      ;
; mc8051_alu_.vhd                  ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/mc8051_alu_.vhd           ;
; dcml_adjust_rtl.vhd              ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/dcml_adjust_rtl.vhd       ;
; dcml_adjust_.vhd                 ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/dcml_adjust_.vhd          ;
; control_mem_rtl.vhd              ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/control_mem_rtl.vhd       ;
; control_mem_.vhd                 ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/control_mem_.vhd          ;
; control_fsm_rtl.vhd              ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/control_fsm_rtl.vhd       ;
; control_fsm_.vhd                 ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/control_fsm_.vhd          ;
; comb_mltplr_rtl.vhd              ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/comb_mltplr_rtl.vhd       ;
; comb_mltplr_.vhd                 ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/comb_mltplr_.vhd          ;
; comb_divider_rtl.vhd             ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/comb_divider_rtl.vhd      ;
; comb_divider_.vhd                ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/comb_divider_.vhd         ;
; alumux_rtl.vhd                   ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/alumux_rtl.vhd            ;
; alumux_.vhd                      ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/alumux_.vhd               ;
; alucore_rtl.vhd                  ; yes             ; User VHDL File                        ; F:/quartusII_example/8051_test/8051_test/alucore_rtl.vhd           ;