mc8051_test.map.rpt

mc8051源码

Analysis & Synthesis report for mc8051_test
Wed Aug 26 09:26:11 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |mc8051_test|mc8051_core:inst|mc8051_control:i_mc8051_control|control_mem:i_control_mem|state
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for mc8051_ramx:inst3|altsyncram:altsyncram_component|altsyncram_oaa1:auto_generated
 15. Source assignments for mc8051_ram:inst2|altsyncram:altsyncram_component|altsyncram_31b1:auto_generated
 16. Source assignments for mc8051_rom:inst1|altsyncram:altsyncram_component|altsyncram_ir21:auto_generated
 17. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu
 18. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|alumux:i_alumux
 19. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|alucore:i_alucore
 20. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|addsub_core:i_addsub_core
 21. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|addsub_core:i_addsub_core|addsub_cy:\gen_greater_four:gen_addsub:4:gen_nibble_addsub:i_addsub_cy
 22. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|addsub_core:i_addsub_core|addsub_ovcy:\gen_greater_four:gen_addsub:5:gen_last_addsub:i_addsub_ovcy
 23. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|comb_mltplr:\gen_multiplier:i_comb_mltplr
 24. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|comb_divider:\gen_divider:i_comb_divider
 25. Parameter Settings for User Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|dcml_adjust:\gen_dcml_adj:i_dcml_adjust
 26. Parameter Settings for User Entity Instance: mc8051_ramx:inst3|altsyncram:altsyncram_component
 27. Parameter Settings for User Entity Instance: mc8051_ram:inst2|altsyncram:altsyncram_component
 28. Parameter Settings for User Entity Instance: mc8051_rom:inst1|altsyncram:altsyncram_component
 29. Parameter Settings for Inferred Entity Instance: mc8051_core:inst|mc8051_alu:i_mc8051_alu|comb_mltplr:\gen_multiplier:i_comb_mltplr|lpm_mult:Mult0
 30. lpm_mult Parameter Settings by Entity Instance
 31. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 26 09:26:11 2009    ;
; Quartus II Version          ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name               ; mc8051_test                              ;
; Top-level Entity Name       ; mc8051_test                              ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 4,369                                    ;
; Total pins                  ; 10                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 66,560                                   ;
; DSP block 9-bit elements    ; N/A until Partition Merge                ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; N/A until Partition Merge                ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C12Q240C8       ;                    ;
; Top-level entity name                                                          ; mc8051_test        ; mc8051_test        ;
; Family name                                                                    ; Cyclone            ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;