VHLD

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--串口通信电路 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sci is port(clksci: in std_logic; rxd: in std_logic; rst: in std_logic; rxdfout: out std_logic; txd: out std_logic; lpt: out std_logic_vector(7 downto 0)); end sci; architecture rtl of sci is signal scir: std_logic_vector(7 downto 0); signal sh_r: std_logic_vector(3 downto 0); signal sl_r: std_logic_vector(3 downto 0); signal scit: std_logic_vector(7 downto 0); signal sh_t: std_logic_vector(3 downto 0); signal sl_t: std_logic_vector(3 downto 0); signal d_fb: std_logic_vector(7 downto 0); signal dfbb: std_logic_vector(7 downto 0); signal dfrxd: std_logic_vector(2 downto 0); signal rxdb: std_logic; signal rxdf: std_logic; signal txdf: std_logic; signal txdcn: std_logic; begin sh_r="1000") and (sh_r

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