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z5w16.vhd
-- output of CoreGen module generator
-- $Header: delayVHT.vhd,v 1.3 1998/06/15 16:02:49 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-1
c_z2chke.c
#include
#include
#include "cblas.h"
#include "cblas_test.h"
int cblas_ok, cblas_lerr, cblas_info;
int link_xerbla=TRUE;
char *cblas_rout;
#ifdef F77_Char
void F77_xerbla(F77_Ch
c_z3chke.c
#include
#include
#include "cblas.h"
#include "cblas_test.h"
int cblas_ok, cblas_lerr, cblas_info;
int link_xerbla=TRUE;
char *cblas_rout;
#ifdef F77_Char
void F77_xerbla(F77_Ch
y_z_jie_space.m
function y_z_jie_space
global X1 X2 X3 b
L2=-(b-1)/2