代码搜索结果

\t (00:00:05) allegro 16.2 p005 (v16-2-57E) i86 \t (00:00:05) \t (00:00:06) Opening existing drawing... \d (00:00:06) Database opened: C:/unnamed.brd \i (00:00:07) trapsize 1828 \i (00:00:07)

\t (00:00:04) allegro 16.2 p005 (v16-2-57E) i86 \t (00:00:04) \t (00:00:05) Opening existing drawing... \d (00:00:05) Database opened: C:/unnamed.brd \i (00:00:05) trapsize 2599 \i (00:00:05)

\t (00:00:00) pad_designer 16.2 p004 (v16-2-57D) i86 \t (00:00:00) \i (00:00:03) setwindow form.padedit \i (00:00:03) pse_new \i (00:00:43) fillin "F:\wenjian\第九章\bu_v_30_15.pad" \i (00:01:09

\t (00:00:03) allegro 15.7 p007 (v15-7-42E) i86 \t (00:00:03) \t (00:00:03) Starting new drawing... \i (00:00:04) trapsize 731 \i (00:00:04) trapsize 857 \i (00:00:04) trapsize 857 \i (00:00:

\t (00:00:07) allegro 15.7 p007 (v15-7-42E) i86 \t (00:00:07) \t (00:00:08) Starting new drawing... \t (00:00:08) Grids are drawn 400.0, 400.0 apart for enhanced viewability. \i (00:00:08) trap

\t (00:00:00) sigwave 15.7 p007 (v15-7-42E) i86 \t (00:00:00) (00:00:00) Loading sigwave.cxt \i (00:00:00) setwindow main \i (00:00:00) deselect all \i (00:00:00) zoom fit \i (00:00:08) s

\t (00:00:00) sigwave 15.7 p007 (v15-7-42E) i86 \t (00:00:00) (00:00:00) Loading sigwave.cxt \i (00:00:00) setwindow main \i (00:00:00) deselect all \i (00:00:00) zoom fit \i (00:00:14) e

\t (00:00:03) allegro 15.7 p007 (v15-7-42E) i86 \t (00:00:03) \t (00:00:03) Opening existing drawing... (00:00:04) Loading signal.cxt \d (00:00:05) Database opened: E:/class_cadence/Minisys

\t (00:00:09) allegro 15.7 p007 (v15-7-42E) i86 \t (00:00:09) \t (00:00:09) Opening existing drawing... \d (00:00:10) Database opened: E:/class_cadence/Minisystem/DSPsystem.brd \t (00:00:10) Gr

\t (00:00:00) sigxp 15.7 p007 (v15-7-42E) i86 \t (00:00:00) \t (00:00:00) Starting new drawing... \t (00:00:00) Grids are drawn 400.0, 400.0 apart for enhanced viewability. \i (00:00:00) trapsi