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t2t.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY T2T IS
PORT
(
data : in std_logic_vector(7 downto 0);
dataout, q
t2t.rpt
Project Information k:\vhdl\n\n\t2t\t2t.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/26/2007 00:05:28
Copyright (C) 1988-2002 Al
t2t.vwf
/*
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edi<mark>t</mark>or if you plan <mark>t</mark>o con<mark>t</mark>inue edi<mark>t</mark>ing <mark>t</mark>he block <mark>t</mark>ha<mark>t</mark> represen<mark>t</mark>s i<mark>t</mark> in
<mark>t< ...
t2t.acf
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
t2t.hex
:020000040000FA
:2B000000FFFF62FF2500FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF76
:2B002B00601886611896611886611986651886611986010000000018866118866118866118866118866
t2t.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
t2t.ndb
NDB006
The number of symbol table entries is: 81
The length of the symbol table is: 6803
Index Hierarchy Path
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