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.module cgi.c .area data(ram, con, rel) _cgitab:: .blkw 1 .area idata .word PL_print_stats .area data(ram, con, rel) .blkw 1 .area idata .word PL_file_stats .area data(ram, con, re

.module uip.c .area lit(rom, con, rel) _uip_hostaddr:: .word 43200 .word 25344 .dbfile D:\hexok项目\AVRNET项目\AVRNET光盘\AVRuIP\uip.c .dbsym e uip_hostaddr _uip_hostaddr A[4:2]ks _uip_arp_drad

.module fsdata.c .area data(ram, con, rel) _file_index_name:: .blkb 2 .area idata .byte 'i,'n .area data(ram, con, rel) .blkb 2 .area idata .byte 'd,'e .area data(ram, con, rel)

.module delay.c .area text(rom, con, rel) .dbfile D:\hexok项目\AVRNET项目\AVRNET光盘\AVRuIP\delay.c .dbfunc e delay_ms _delay_ms fV ; delay_count -> R10,R11 ; delay_cnt -> R10,R11 ; delay_

.module httpd.c .area text(rom, con, rel) .dbfile D:\hexok项目\AVRNET项目\AVRNET光盘\AVRuIP\httpd.c .dbfunc e httpd_init _httpd_init fV .even _httpd_init:: .dbline -1 .dbline 184 ; /** ; *

.module fs.c .area data(ram, con, rel) _file_index_name:: .blkb 2 .area idata .byte 'i,'n .area data(ram, con, rel) .blkb 2 .area idata .byte 'd,'e .area data(ram, con, rel) .blk

.module main.c .area text(rom, con, rel) .dbfile D:\hexok项目\AVRNET项目\AVRNET光盘\AVRuIP\main.c .dbfunc e initTimer _initTimer fV .even _initTimer:: .dbline -1 .dbline 57 ; /***************

;/****************************************Copyright (c)************************************************** ;** Guangzou ZLG-MCU Development Co.,LTD. ;**

;/****************************************Copyright (c)************************************************** ;** Guangzou ZLG-MCU Development Co.,LTD. ;**

;;; Copyright ARM Ltd 2001. All rights reserved. AREA Stacks, DATA, NOINIT EXPORT UserStack EXPORT SVCStack EXPORT UndefStack EXPORT IRQStack