代码搜索结果

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation,

MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR= 05,03,03,04,03,03,05,04, 04,04,05,05,05,06,07,0D, 08,07,07,07,07,10,0B,0C, 09,0D,13,10,14,13,12,10, 12,12,15,17,1E,19,15,16, 1C,16,12,12,1

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation,

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 10 13 6 36 37) (author "Xilinx, Inc.") (program "Xilinx CORE Generator" (version "Xili

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation,

0110011001101 1010101010101 1010101010101 0110011001101 0100100100101 0010011101100 0010000000000 0001100110011 1010101010101 1010101010101 1000000000000 0101010101011 0100000000000 0001101011110 0001

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation,