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usb_new_rcv_ram_ent.vhdl
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-- P H I L I P S C O M P A N Y R E S T R I C T E D
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-- Copyright
usb_new_usb_int_str.vhdl
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--
-- P H I L I P S C O M P A N Y R E S T R I C T E D
--
-- Copyright
wch_fht.plg
@P: Part : EP1C3TC100-6
@P: Worst Slack : 994.975
@P: wch_fht|Clk - Estimated Frequency : 199.0 MHz
@P: wch_fht|Clk - Requested Frequency : 1.0 MHz
@P: wch_fht|Clk - Estimated Period : 5.025
fhtpart.plg
@P: Part : EP1C3TC100-6
@P: Worst Slack : 995.896
@P: fhtpart|Clk - Estimated Frequency : 243.7 MHz
@P: fhtpart|Clk - Requested Frequency : 1.0 MHz
@P: fhtpart|Clk - Estimated Period : 4.104
generator.plg
@P: Part : EP1S25FC780-5
@P: Worst Slack : 994.665
@P: generator|CLK - Estimated Frequency : 187.4 MHz
@P: generator|CLK - Requested Frequency : 1.0 MHz
@P: generator|CLK - Estimated Period :
control.plg
@P: Worst Slack : 475.100
@P: alea - Estimated Frequency : 54.9 MHz
@P: alea - Requested Frequency : 1.0 MHz
@P: alea - Estimated Period : 18.200
@P: alea - Requested Period : 1000.000
@P:
fpga_core.plg
@P: Worst Slack : -10.338
@P: fpga_core|clk_48 - Estimated Frequency : 52.4 MHz
@P: fpga_core|clk_48 - Requested Frequency : 100.0 MHz
@P: fpga_core|clk_48 - Estimated Period : 19.079
@P: fpg
p.bat
set path=c:\iverilog\bin
@rem iverilog -oa86_tb_disasm a86_tb_disasm.v
iverilog -yc:\iverilog\rom\ -oa86_tb a86_tb.v
rem vvp a86_tb
iverilog -oa86_alu_bmux a86_alu_bmux.v
uart4.plg
@P: Worst Slack : 492.792
@P: Uart4|clk - Estimated Frequency : 69.4 MHz
@P: Uart4|clk - Requested Frequency : 1.0 MHz
@P: Uart4|clk - Estimated Period : 14.417
@P: Uart4|clk - Requested Peri
top.plg
@P: Worst Slack : -4.439
@P: TOP|CLK - Estimated Frequency : 444.7 MHz
@P: TOP|CLK - Requested Frequency : 100.0 MHz
@P: TOP|CLK - Estimated Period : 2.249
@P: TOP|CLK - Requested Period : 10