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A 的代码
sigsimres.dat
A!simid!rcvr!cycle!nmhigh!nmhighcycle!nmlow!nmlowcycle!prop!switchhigh!switchlow!settlehigh!settlelow!maxvoltage!maxvoltagecycle!minvoltage!minvoltagecycle!monotonichigh!monotoniclow!glitchrise!glitch
sim1.sim
A!Time!Node!Potential!NodeName!
S!0!2!5.35712e-006!123.U4.1!
S!0!3!5.35712e-006!123.U4.24!
S!0!1!5.35711e-006!123.R2.2!
S!2.5e-010!2!0.0467971!123.U4.1!
S!2.5e-010!3!5.35716e-006!123.U4.24!
S!2.
distortion.dst
A!Node!VssInitial!VssFinal!VMax!TMax!VMin!TMin!NodeName1!NodeName2!..!
S!1!5.35711e-006!0!2.60406!4.285e-008!-0.101386!1.285e-008!123.R2.2!
S!2!5.35712e-006!0!2.97833!1.75e-009!-0.467165!1.16e-008!1
delay.dl
A!Node!tldelay!ToLo!ToHi!ToHalf!ToRef!ToSettle!Vlomax!Vhimin!Vhalf!Vref!Vsettle!TNonMonotonic!VNonMonotonic!NodeName1!NodeName2!..!
S!1!0!!!!!!!!!!!!!123.R2.2!
S!2!1.1962e-010!!!!!!!!!!!!!123.U4.1!
sigsimcntl.dat
A!drvr!activercvr!stimulus!ftsmode!simtype!testvector!switchingmode!waveform!simid!
S!123 R2 2!!P!T!R!!!1!sim1!
sigsimres.dat
A!simid!rcvr!cycle!nmhigh!nmhighcycle!nmlow!nmlowcycle!prop!switchhigh!switchlow!settlehigh!settlelow!maxvoltage!maxvoltagecycle!minvoltage!minvoltagecycle!monotonichigh!monotoniclow!glitchrise!glitch
sigsimcntl.dat
A!drvr!activercvr!stimulus!ftsmode!simtype!testvector!switchingmode!waveform!simid!
a.opj
(ExpressProject "a"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\a.dsn"
(Type "Schematic Design"))