代码搜索结果

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY seg70 IS PORT ( clk : IN std_logic; rst

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Flow report for seg70 Mon Feb 16 22:20:08 2009 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 pt

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

Fitter report for seg70 Mon Feb 16 22:20:03 2009 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fi

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

Analysis & Synthesis report for seg70 Mon Feb 16 22:19:57 2009 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal N

Mon Feb 16 22:20:09 2009