代码搜索结果

"8.5.c" BROWSE DEBUG OBJECTEXTEND

"8.3.c" BROWSE DEBUG OBJECTEXTEND

"8-isd4004.obj" TO "8-isd4004"

/*8-2.c*/ #include"time.h" #include "dos.h" char far *buf; void (interrupt far *oldintfun)(); struct time t; union REGS i,o; void interrupt far newintfun() { static int time1=0,count=0; time

/*8-1.c*/ #include #include #include #include #include #define INTR 0x1c void interrupt ( *oldhandler) (); int fre[]={523,659,587,659,587,49

-- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std_logic_1164.all; entity HCT688 is port(Q, P : in std_logic_v

|8 clk7279 hd7279:inst.CLK clk => ADC0809:inst3.clk RST_N => hd7279:inst.RST_N RST_N => ADC0809:inst3.RST_N key7279 => hd7279:inst.key7279 dat7279

8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流 library ieee; use ieee.std_logic_1164.all; entity fifo is generic( w: integer :=8; k: integer :=8 ); port (cl

-- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std_logic_1164.all; entity HCT688 is port(Q, P : in std_logic_v

//8阶对称系数并行FIR滤波器 module fir(clk,rst,fir_in,fir_out); parameter IDATA_WIDTH=12; parameter PDATA_WIDTH=13; parameter FIR_TAP=8; parameter FIR_TAPHALF=4; parameter COEFF_WIDTH=12; parameter OUT_