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decl7s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S IS
PORT (A :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE ONE OF DECL7S IS
BEG
decl7s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S IS
PORT (A :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE ONE OF DECL7S IS
BEG
frequency.tbl
%
Copyright (C) 1991-2005 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
cnt60.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
main.txt
; generated by ARM/Thumb C/C++ Compiler with Crescent Bay VAST 10.7u+w+:x ARM NEON, RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\obj\main.o --depend=..\obj\