代码搜索结果

%FSLAX23Y23*% %MOIN*% G70* G01* G75* G04 Layer_Physical_Order=1* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD

[ C1 RAD0.2 0.1uF ] [ C2 RAD0.2 0.1uF ] [ C3 RAD0.2 0.1uF ] [ C4 RAD0.2 0.1uF ] [ C5 RAD0.2 0.1uF ] [ C8 RAD0.2 0.1uF ] [ C9 RAD0.2

Layer Pairs Export File for PCB: C:\Program Files\Altium\Examples\4 Port Serial Interface\4 Port Serial Interface.PcbDoc LayersSetName=Top_Bot_Thru_Holes|DrillFile=txt|LayerPairs=gtl,gbl

%FSLAX23Y23*% %MOIN*% G70* G01* G75* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD17C,0.062*% %ADD18C,0.150*%

%FSLAX23Y23*% %MOIN*% G70* G01* G75* G04 Layer_Physical_Order=2* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD

%FSLAX23Y23*% %MOIN*% G70* G01* G75* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD17C,0.062*% %ADD18C,0.150*%

DRC Rules Export File for PCB: C:\Program Files\Altium\Examples\4 Port Serial Interface\4 Port Serial Interface.PcbDoc RuleKind=Width|RuleName=All|Scope=Board|Minimum=10.00 RuleKind=SolderMaskExpans

%FSLAX23Y23*% %MOIN*% G70* G01* G75* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD17C,0.062*% %ADD18C,0.150*%

%FSLAX23Y23*% %MOIN*% G70* G01* G75* %ADD10O,0.050X0.300*% %ADD11C,0.009*% %ADD12C,0.010*% %ADD13C,0.020*% %ADD14C,0.006*% %ADD15C,0.008*% %ADD16C,0.012*% %ADD17C,0.062*% %ADD18C,0.150*%

(edif &4_Port_Serial_Interface_PRJPCB (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0) ) (status (written (timeStamp 2004 6 23 20 12 52) (program