代码搜索:4

找到约 10,000 项符合「4」的源代码

代码结果 10,000
www.eeworm.com/read/160253/10548961

m example4_2_4.m

load noisbloc x = noisbloc; t = wpdec(x,3,'sym4'); plot(t); %在运行上面命令出现的图形窗口中将Node Label从Depth-postion切换到 %Index并单击索引值为0的结点,即根结点,如图4-9所示 %全局阈值处理 t1 = t; sorh = 'h'; %硬阈值 thr = wthrmngr('wp1d
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bak 4-4_uv2.bak

### uVision2 Project, (C) Keil Software ### Do not modify ! Target (Target 1), 0x0000 // Tools: 'MCS-51' Group (Source Group 1) File 1,2, 0x0 File 1,1,
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m improveab4_am4.m

function improveAB4_AM4(h,x0,xn,y0) N=(xn-x0)/h; N=round(N); x=zeros(1,N+1); yp=zeros(1,N+1); yc=zeros(1,N+1); y=zeros(1,N+1); for i=0:N x(i+1)=x0+h*i; end y(1)=y0; for i=1:3 k
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m ab4_am4.m

function AB4_AM4(h,x0,xn,y0) N=(xn-x0)/h; N=round(N); x=zeros(1,N+1); yp=zeros(1,N+1); y=zeros(1,N+1); for i=0:N x(i+1)=x0+h*i; end y(1)=y0; for i=1:3 k1=f(x(i),y(i)); k2=f
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v mult4x4.v

module mult4x4(out,a,b,clk); output[7:0] out; input[3:0] a,b; input clk; reg[7:0] out; reg[1:0] firsta,firstb; reg[1:0] seconda,secondb; wire[3:0] outa,outb,outc,outd; always @(posedge clk)
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v mult4x4.v

module mult4x4(out,a,b,clk); output[7:0] out; input[3:0] a,b; input clk; reg[7:0] out; reg[1:0] firsta,firstb; reg[1:0] seconda,secondb; wire[3:0] outa,outb,outc,outd; always @(posedge clk)
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bak 4_2_4_opt.bak

### uVision2 Project, (C) Keil Software ### Do not modify ! cExt (*.c) aExt (*.a*; *.src) oExt (*.obj) lExt (*.lib) tExt (*.txt) pExt (*.plm) DaveTm { 0,0,0,0,0,0,0,0 } Target (Tar
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cpp shiti9_4_4.cpp

#include class Base1 { public: Base1(int x){cout
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txt 试题9-4-4.txt

#include class Base1 { public: Base1(int x){cout
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ncb shiti9_4_4.ncb