代码搜索结果

找到约 23,033 项符合 4 的代码

4.3.lnp

"4.3.4.obj" TO "4.3.4"

jiexiao10

<mark>4</mark>.728575 <mark>4</mark>.75<mark>4</mark>822 <mark>4</mark>.7793<mark>4</mark>5 <mark>4</mark>.802173 <mark>4</mark>.823330 <mark>4</mark>.8<mark>4</mark>2862 <mark>4</mark>.86081<mark>4</mark> <mark>4</mark>.877200 <mark>4</mark>.892095 <mark>4</mark>.905522 <mark>4</mark>.917539 <mark>4</mark>.928192 <mark>4</mark>.937530 <mark>4</mark>.9<mark>4</mark>5607 <mark>4</mark>.952<mark>4</ ...

jiexiao11

<mark>4</mark>.728575 <mark>4</mark>.75695<mark>4</mark> <mark>4</mark>.7836<mark>4</mark>8 <mark>4</mark>.808680 <mark>4</mark>.832036 <mark>4</mark>.8537<mark>4</mark>1 <mark>4</mark>.873808 <mark>4</mark>.8922<mark>4</mark>2 <mark>4</mark>.909080 <mark>4</mark>.92<mark>4</mark>318 <mark>4</mark>.937999 <mark>4</mark>.950118 <mark>4</mark>.960735 <mark>4</mark>.969852 <mark>4</mark>.977<mark>4</ ...

4 位数字频率计控制模块.txt

4 位数字频率计控制模块 module fre_ctrl(clk,rst,count_en,count_clr,load); output count_en,count_clr,load; input clk,rst; reg count_en,load; always @(posedge clk) begin if(rst) begin count_en=0; load=1; en