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找到约 10,000 项符合「2」的源代码
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sdc prep2_2.sdc
# The following property will prevent
# Synplify from putting an HCLKBUF
# on the CLK port.
# A CLKINT will still be inserted on
# The reset line.
define_attribute CLK syn_noclockbuf 1
# Also se
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prj prep2_2.prj
#-- Synplicity, Inc.
#-- Version 7.2 Beta
#-- Project file E:\work\syn720\examples\vhdl\qlogic\prep2_2.prj
#-- Written on Tue Aug 20 16:39:20 2002
#add_file options
add_file -constraint
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sdc prep2_2.sdc
# Request that the Port SEL use an "BIDIR" pad type
define_attribute SEL ql_padtype "BIDIR"
# Assign placement locations to all bits of the bus.
define_attribute {DATA0[7:0]} ql_placement "IO7,IO6,
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prj prep2_2.prj
#-- Synplicity, Inc.
#device options
set_option -technology STRATIX
set_option -part EP1S10
set_option -package FC780
set_option -speed_grade -5
#add_file options
add_file -constraint "prep
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sdc prep2_2.sdc
# Put a scalar signal on a pad location 159
define_attribute SEL altera_chip_pin_lc "@159"
# Assign pad locations to all bits of a bus
define_attribute {DATA0[7:0]} altera_chip_pin_lc "@120,@121,@1
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prj prep2_2.prj
#-- Synplicity, Inc.
#device options
set_option -technology VIRTEX
set_option -part XCV50
set_option -package FG256
set_option -speed_grade -4
#add_file options
add_file -vhdl -lib work "..
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sdc prep2_2.sdc
# Assign a location for scalar Port "SEL".
define_attribute SEL xc_loc "C13"
# Assign a pad location to all bits of a bus.
define_attribute {DATA0[7:0]} xc_loc "P14, P12, P11, P5, P21, P18, P16, P
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prj prep2_2.prj
#-- Synplicity, Inc.
#-- Synplify version 3.0
#-- Project file V:\rel\latest\examples\vhdl\lucent\prep2_2.prj
#-- Written on Tue Jul 15 18:53:46 1997
#device options
set_option -technology orca
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sdc prep2_2.sdc
# Request that the Port "SEL" use an IBT pad type
define_attribute SEL orca_padtype "IBT"
# Tell Foundary that register should be close to the pad for all bits of a bus
define_attribute {DATA0[7:0]
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