代码搜索:2

找到约 10,000 项符合「2」的源代码

代码结果 10,000
www.eeworm.com/read/405978/11452009

pin freq2_2.pin

-- Copyright (C) 1991-2008 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a
www.eeworm.com/read/405978/11452015

qws freq2_2.qws

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 pt
www.eeworm.com/read/405978/11452016

qsf freq2_2.qsf

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
www.eeworm.com/read/405978/11452019

sft freq2_2.sft

set tool_name "ModelSim (Verilog)" set corner_file_list { {{"Slow Model"} {freq2_2.vo freq2_2_v.sdo}} }
www.eeworm.com/read/405978/11452021

vo freq2_2.vo

// Copyright (C) 1991-2008 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any o
www.eeworm.com/read/405978/11452023

qpf freq2_2.qpf

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
www.eeworm.com/read/405978/11452024

done freq2_2.done

Sun Dec 21 15:20:10 2008
www.eeworm.com/read/405978/11452025

v freq2_2.v

module freq2_2(//input clk, //output freq2_2 ); input clk; output reg freq2_2; reg [2:0] count,freq; always@(posedge clk) begin count
www.eeworm.com/read/405978/11452027

sof freq2_2.sof

www.eeworm.com/read/405978/11452030

pof freq2_2.pof