Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
标签： Converters Defini DAC
上传时间： 2013-10-29
上传用户：stvnash
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间： 2013-11-11
上传用户：pans0ul
分析了调幅信号和载波信号之间的相位差与调制信号的极性的对应关系,得出了相敏检波电路输出电压的极性与调制信号的极性有对应关系的结论。为了验证相敏检波电路的这一特性,给出3 个电路方案,分别选用理想元件和实际元件,采用Multisim 对其进行仿真实验,直观形象地演示了相敏检波电路的鉴相特性,是传统的实际操作实验所不可比拟的。关键词:相敏检波;鉴相特性;Multisim;电路仿真 Abstract : The corresponding relation between modulation signal polarity and difference phases of amplitudemodulated signal and the carrier signal ,the polarity of phase2sensitive detecting circuit output voltage and the polarity of modulation signal are correspondent . In order to verify this characteristic ,three elect ric circuit s plans are produced ,idea element s and actual element s are selected respectively. Using Multisim to carry on a simulation experiment ,and then demonst rating the phase detecting characteristic of the phase sensitive circuit vividly and directly. Which is t raditional practical experience cannot be com pared.Keywords :phase sensitive detection ;phase2detecting characteristic ;Multisim;circuit simulation
上传时间： 2013-11-23
上传用户：guanhuihong
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
标签： Synplicity Machine Verilog Design
上传时间： 2013-10-23
上传用户：司令部正军级
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-10-08
上传用户：wangzhen1990
该系统由单片机89S52控制模块，程控宽带放大模块，整形模块，FPGA内频率、相位差测量模块等构成，采用等精度测频法测出频率和周期，可测量有效值为0.01～5V，频率范围1Hz～20MHz信号的频率、周期信号，精度高达10-6。采用计数法测量相位差，该系统可测量有效值0.5～5V，频率10Hz～100kHz信号的相位差，精度为1°。系统功能由按键控制，测量结果实时显示，人机界面友好。 Abstract: The system consists of the following functional blocks:89S52microcontroller controlling module,programmable amplifier module,comparator module,frequency and phase difference testing module in the FPGA.The system use the equal accuracy frequency-examining technique it measures frequency and circle of signal which its ranges is from1Hz to20MHz and the amplitude of which its range is from0.01Vrms to5Vrms,precision is up to10-6.Using of count method,the system detects the phase difference of signal,the amplitude of whic its range is from0.5Vrms to5Vrms and the frequency of which its ranges is from10Hz to100kHz,precision is up to1°,The system functions is controlled by certain keys,measurement results are displayed in real-time and it is friendly interface.
上传时间： 2013-11-04
上传用户：CHINA526
以89S52单片机和EP1C6Q240C8型FPGA为控制核心的多功能计数器，是由峰值检波、A/D转换、程控放大、比较整形、移相网络部分组成,可实现测量正弦信号的频率、周期和相位差的功能。多功能计数器采用等精度的测量方法，可实现频率为1Hz～10MHz、幅度为0.01～5Vrms的正弦信号的精确测频，以及频率为10Hz～100kHz、幅度为0.5～5Vrms的正弦信号精确测相。液晶显示器能够实时显示当前信号的频率、周期和相位差。该多功能计数器精度高，界面友好，实用性强。 Abstract: A multi-function counter，which uses89S52MCU and EP1C6Q240C8FPGA as a control core，consists of peak detector，A/D conversion，program-controlled amplification，compared shaping and phase-shifting network part.The counter measures the frequency，period and phase of sinusoidal signal.With the equal precision method,the multi-function counter achieves the precise frequency measurement of the sinusoidal signal which its frequency is from1Hz to10MHz，its amplitude is from0.01Vrms to5Vrms，as well as the accurate phase measurement of the sinusoidal signal which its frequency is from10Hz to100kHz，its amplitude is from0.5Vrms to5Vrms.The LCD monitor real-time displays the frequency，period and phase difference of current signal.The multi-function counter features high precision，friendly interface，and strong practical.
上传时间： 2013-11-14
上传用户：gy592333
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上传时间： 2013-10-26
上传用户：zhangyigenius
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2014-01-12
上传用户：qoovoop
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
标签： Synplicity Machine Verilog Design
上传时间： 2013-10-20
上传用户：苍山观海
