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VC书籍  jin tian xin qing hen hao nimen kuaikuai xiazai

jin tian xin qing hen hao nimen kuaikuai xiazai

https://www.eeworm.com/dl/686/199731.html

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Applet 高考信息系统 gao kao xin xi xi tong JAVA

高考信息系统 gao kao xin xi xi tong JAVA

https://www.eeworm.com/dl/634/215589.html

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其他  xin xi

xin xi

https://www.eeworm.com/dl/534/226344.html

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串口编程  chuan kou tong xin de shi xian

chuan kou tong xin de shi xian

https://www.eeworm.com/dl/624/278397.html

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编译器/解释器  de hoan thanh bai tap toi da rat vat va, mong cac ban xem va gop y kien , xin cam on

de hoan thanh bai tap toi da rat vat va, mong cac ban xem va gop y kien , xin cam on

https://www.eeworm.com/dl/628/481381.html

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书籍源码  //* * * * * * * * * * * * *** // MSP430x1xx Demo - Software Toggle P1.0 /

//*** *** *** *** *** *** *** *** *** *** *** *** *** // MSP430x1xx Demo - Software Toggle P1.0 // // Description Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO // // MSP430x1xx // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // ...

https://www.eeworm.com/dl/532/232351.html

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单片机开发  //* * * * * * * * * * * * *** * // MSP-FET430x110 Demo - Software Toggle P1

//*** *** *** *** *** *** *** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1.0 // // Description: Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO ~800k // // MSP430F1121 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT ...

https://www.eeworm.com/dl/648/305404.html

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Java编程  清华大学第二版

清华大学第二版，xin yun wei ma suxia 等人

https://www.eeworm.com/dl/633/314892.html

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单片机开发  Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Ech

Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & X ...

https://www.eeworm.com/dl/648/361145.html

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VHDL/FPGA/Verilog it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin

it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

https://www.eeworm.com/dl/663/418186.html

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