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操作系统开发 a fat12 source code, it is verified for many platform
a fat12 source code, it is verified for many platform
行业发展研究 Pre-designed and pre-verified hardware and software blocks can be combined on chips for many differ
Pre-designed and pre-verified hardware and software blocks can be combined on
chips for many different applicationsVthey promise large productivity gains.
其他书籍 PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. Th
PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this boo ...
汇编语言 wireless stepper motor verified by kpserver
wireless stepper motor verified by kpserver
DSP编程 基于DSP Builder数字信号处理器的FPGA设计
针对使用硬件描述语言进行设计存在的问题，提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程，设计了一个12阶FIR 低通数字滤波器，通过Quartus 时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明，所设计的FIR 滤波 ...
其他 BlueCore supports a mechanism called Device Firmware Upgrade (DFU) to enable its software and config
BlueCore supports a mechanism called Device Firmware Upgrade (DFU) to enable its software and configuration data to be replaced. To guard against unauthorised changes, downloaded files can be verified by means of signatures.
The DFU Tools are a suite of programs that enable firmware and persistent ...
压缩解压 THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EX
THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been ver ...
VHDL/FPGA/Verilog The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.
matlab例程 This chapter contains sample programs for determining capacity. The reader is advised to go through
This chapter contains sample programs for determining capacity. The reader is advised to go through the coding. The
file "capacity_water.m" is for measuring the waterfilling capacity. It should be made to work with a file similar to
"capacity_plot_main.m". The latter file deals with all the other c ...
GPS编程 This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of each ch
This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of
each channel. The preamble is verified by check of the spacing between
preambles [6sec] and parity checking of the first two words in a
subframe. At the same time function returns list of channels, that a ...