Software-defined radios (SDRs) have been around for more than a decade. The first complete Global Positioning System (GPS) implementation was described by Dennis Akos in 1997. Since then several research groups have presented their contributions. We therefore find it timely to publish an up-to-date text on the sub- ject and at the same time include Galileo, the forthcoming European satellite- based navigation system. Both GPS and Galileo belong to the category of Global Navigation Satellite Systems (GNSS).
标签： A_Software-Defined_GPS_and_Galile o_Receiver
上传时间： 2020-06-09
上传用户：shancjb
The purpose of this book is to present detailed fundamental information on a global positioning system (GPS) receiver. Although GPS receivers are popu- larly used in every-day life, their operation principles cannot be easily found in one book. Most other types of receivers process the input signals to obtain the necessary information easily, such as in amplitude modulation (AM) and frequency modulation (FM) radios. In a GPS receiver the signal is processed to obtain the required information, which in turn is used to calculate the user position. Therefore, at least two areas of discipline, receiver technology and navigation scheme, are employed in a GPS receiver. This book covers both areas.
标签： Fundamentals_of_Global_Positionin g_System_Receivers
上传时间： 2020-06-09
上传用户：shancjb
If one examines the current literature on GPS receiver design, most of it is quite a bit above the level of the novice. It is taken for granted that the reader is already at a fairly high level of understanding and proceeds from there. This text will be an attempt to take the reader through the concepts and circuits needed to be able to understand how a GPS receiver works from the antenna to the solution of user position.
标签： Fundamentals_of_Global_Positionin g_System
上传时间： 2020-06-09
上传用户：shancjb
Of the various applications that satellites have been used for, one of the most promising is that of global positioning. Made possible by Global Navigation Satellite Systems, global positioning enables any user to know his or her exact position on Earth. Nowadays, the only fully functioning system is the American Global Positioning System (GPS). However, the European system, known as Galileo, is expected to be operative in 2012.
上传时间： 2020-06-09
上传用户：shancjb
EES_REFPROP源码，User Instructions for EES_REFPROP
上传时间： 2021-08-24
上传用户：18868103493
FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
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MSP430f249单片机文档资料+软件DEMO程序50例程合集:MSP430f249 用户手册.pdfmsp430x24x_1msp430x24x_1_vlomsp430x24x_adc12_01msp430x24x_adc12_02msp430x24x_adc12_03msp430x24x_clksmsp430x24x_compA_01msp430x24x_compA_02msp430x24x_compA_04msp430x24x_compA_05msp430x24x_dco_flashcalmsp430x24x_flashwrite_01msp430x24x_flashwrite_02msp430x24x_flashwrite_03msp430x24x_fll_01msp430x24x_fll_02msp430x24x_hfxt2msp430x24x_hfxt2_nmimsp430x24x_lpm3msp430x24x_lpm3_vlomsp430x24x_MPY_01msp430x24x_MPY_02msp430x24x_nmimsp430x24x_OF_LFXT1msp430x24x_OF_XT2msp430x24x_P1_01msp430x24x_P1_02msp430x24x_P1_05msp430x24x_roscmsp430x24x_svs_01msp430x24x_ta_01msp430x24x_ta_02msp430x24x_tb_10msp430x24x_uscia0_irda_01msp430x24x_uscia0_irda_02msp430x24x_uscia0_irda_03msp430x24x_uscia0_spi_01msp430x24x_uscia0_uart_01_115kmsp430x24x_uscia0_uart_01_115k_lpmmsp430x24x_uscia0_uart_01_19200msp430x24x_uscia0_uart_01_9600msp430x24x_uscia0_uart_04_9600msp430x24x_uscia0_uart_05_9600msp430x24x_uscia0_uart_06_9600msp430x24x_uscia0_uart_07_9600msp430x24x_uscia0_uart_08_9600msp430x24x_uscia1_irda_01msp430x24x_uscia1_spi_09msp430x24x_uscia1_spi_10msp430x24x_uscia1_uart_05_9600msp430x24x_uscib0_i2c_01msp430x24x_uscib0_i2c_02msp430x24x_uscib0_i2c_04msp430x24x_uscib0_i2c_05msp430x24x_uscib0_i2c_06msp430x24x_uscib0_i2c_07msp430x24x_uscib0_i2c_08msp430x24x_uscib0_i2c_09msp430x24x_uscib0_i2c_10msp430x24x_uscib0_i2c_11msp430x24x_uscib0_i2c_15msp430x24x_uscib0_spi_01msp430x24x_uscib0_spi_02msp430x24x_uscib0_spi_09msp430x24x_uscib0_spi_10msp430x24x_uscib1_i2c_06msp430x24x_uscib1_i2c_07msp430x24x_uscib1_spi_09msp430x24x_uscib1_spi_10msp430x24x_wdt_01msp430x24x_wdt_02msp430x24x_wdt_04msp430x24x_wdt_05msp430x24x_wdt_06MSP430x2xx Family User's Guide.pdf
标签： msp430f249 单片机
上传时间： 2021-11-03
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IIC接口E2PROM(AT24C64) 读写VERILOG 驱动源码+仿真激励文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM从机地址 parameter CLK_FREQ = 26'd50_000_000, //模块输入的时钟频率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的时钟频率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C触发执行信号 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C读写控制信号 input [15:0] i2c_addr , //I2C器件内地址 input [ 7:0] i2c_data_w , //I2C要写的数据 output reg [ 7:0] i2c_data_r , //I2C读出的数据 output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C应答标志 0:应答 1:未应答 output reg scl , //I2C的SCL时钟信号 inout sda , //I2C的SDA信号 //user interface output reg dri_clk //驱动I2C操作的驱动时钟 );//localparam definelocalparam st_idle = 8'b0000_0001; //空闲状态localparam st_sladdr = 8'b0000_0010; //发送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //发送16位字地址localparam st_addr8 = 8'b0000_1000; //发送8位字地址localparam st_data_wr = 8'b0001_0000; //写数据(8 bit)localparam st_addr_rd = 8'b0010_0000; //发送器件地址读localparam st_data_rd = 8'b0100_0000; //读数据(8 bit)localparam st_stop = 8'b1000_0000; //结束I2C操作//reg definereg sda_dir ; //I2C数据(SDA)方向控制reg sda_out ; //SDA输出信号reg st_done ; //状态结束reg wr_flag ; //写标志reg [ 6:0] cnt ; //计数reg [ 7:0] cur_state ; //状态机当前状态reg [ 7:0] next_state; //状态机下一状态reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //读取的数据reg [ 7:0] data_wr_t ; //I2C需写的数据的临时寄存reg [ 9:0] clk_cnt ; //分频时
标签： iic 接口 e2prom at24c64 verilog 驱动 仿真
上传时间： 2021-11-05
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全志A33芯片资料A33核心板技术手册硬件参考设计A33开发板CADENCE原理图PADS PCB图文件：A33 brief 20140522.pdfA33 Datasheet release1.0.pdfA33 user manual release 1.0.pdfA33-Core3引脚定义表.pdfA33-Core3核心板外围电路设计参考.pdfA33-Core3核心板硬件手册.pdfA33_Vstar3使用手册VerC.pdf尺寸图底板PCB图开发底板原理图PCB网卡电路参考设计说明.txtA33-Core3引脚图.pdfA33-Vstar-LCD07-10.pdfRER-A33-DVK3-padslogic95.schRER-A33-DVK3-SCH.DSNRER-A33-DVK3-SCH.pdf第二版改MIPI座子
上传时间： 2021-11-08
上传用户：qdxqdxqdxqdx
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
上传时间： 2021-11-09
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